As designers seek to pack ever-more transistors into smaller spaces, SoC size is nearing the reticle ceiling for manufacturing. In short, traditional monolithic SoCs are becoming too big and costly to produce for advanced designs, and yield risk grows along with design size. Disaggregating SoC components, manufacturing them separately, and then bringing those distinct functions together in a single package results in less waste. The goal is to reduce cost and greatly improve reliability by assembling only known good dies in the package.
Aside from supporting different components on different process nodes that are optimal for the particular function, a multi-die architecture also allows integration of dies from digital, analog, or high-frequency processes. You can also incorporate highly dense three-dimensional memory arrays, High-Bandwidth Memory (HBM), within your design.
Let’s say you are developing a device that might not need the most advanced process for your I/O interfaces, such as Ethernet interfaces, but perhaps you do for your co-processors. By manufacturing on the node that’s appropriate for the function, you optimize your PPA at a granular, form-follows-function level. And if you use the same I/O subsystem across devices, for example in products that differentiate features across tiers, you can get economy of scale, manufacturing all the I/O interfaces at once. Compare this with monolithic design, where the entire SoC is on the same die, regardless of the function. This means your I/O interfaces are running on the same process as your most advanced capabilities, and if one component of the design fails, it all fails.
The scale and modular flexibility will also help you meet narrowing time-to-market windows. Dies with standard functions can be mixed and matched—a kind of hard IP—allowing your engineering talent to focus on the differentiating factors of your design, speeding delivery to market.
While all of this may sound great, disaggregated dies introduce a higher level of complexity in terms of bandwidth, interoperability, and data integrity. Because of this, multi-die designs have been the purview of larger players who have the resources to support custom interconnect development between the dies. But as this newer design methodology has gained traction, the bespoke nature of die-to-die interconnects has been at odds with interoperability. Despite these challenges, the chiplet market is expected to grow to $50B by 2024. And UCIe is a key enabler for this growth.