Synopsys PCIe Leadership Recognized: Paul Cassidy Joins a Track Record of PCI-SIG Contribution

At this year's PCI-SIG® Developers Conference, Synopsys' Paul Cassidy, a senior PCIe architect and long-time Protocol Working Group contributor, received the PCI-SIG Chairperson's Award. He joins Richard Solomon, PCI-SIG Vice President and longtime specification leader recognized in 2022, and Scott Knowlton, chair of the PCI-SIG Marketing Workgroup and recognized in 2023, continuing a multi-year pattern of Synopsys leadership being recognized by the consortium.

Three awards in five years is not coincidence. It reflects a sustained, hands-on influence on how PCI Express™ (PCIe™) evolves, from early specification work to ecosystem validation and deployment.

The PCI-SIG Chairperson's Award is not given for marketing reasons. It's given to engineers who consistently contribute to the standard itself by actively participating in working groups, technical reviews, and ecosystem enablement.

Paul's contributions center on the Protocol Working Group (PWG), where the upper layers of PCIe behavior are defined. While other workgroups focus on the electrical signaling and various mechanical form-factors, Paul and the other PWG members work on the details of most everything else—from link initialization and flow control, to packet formats, error handling, and high-level feature interaction. It's at the uppermost "transaction layer" where most implementers see "spec language" turning into real system behavior. Paul has done more than just participate in developing the specifications, though; he's also traveled around the world educating PCI-SIG members on them at PCI-SIG Developers Conferences.

And like most recipients, Paul's reaction was simple: genuine surprise.

That's because this work isn't flashy. It's iterative, collaborative, and happens over years—reviewing sections of the spec, contributing feedback, presenting at Developers Conferences, and generally helping the broader ecosystem stay aligned. Paul's modestly explained that many times he's the public face of the work done by many Synopsys engineers on his and other teams.

PCIe doesn't come from one company. It comes from PCI-SIG—a consortium where hundreds of companies contribute to a shared standard that underpins nearly every modern compute system.

The work is divided across multiple groups, for example:

• The Electrical Working Group defines the myriad of parameters controlling how signals actually move and are processed at today's staggeringly fast data rates
• The Protocol Working Group defines upper layer behavior which encapsulates and moves data while ensuring its reliable delivery
• The Serial Enabling Group defines PCI-SIG Compliance workshops, helping ensure interoperability of products across the entire PCIe ecosystem
• And newer efforts, like the PCI-SIG Optical Workgroup, are extending PCIe into next-generation interconnects

This is what makes work on standards different. It's not just defining the future; it's making sure that future can actually be built.

Synopsys is deeply embedded in the process of defining each new generation of PCI Express and has been for many years.

More than 50 Synopsys engineers contribute across PCI-SIG working groups, covering protocol, electrical, compliance, optical, and more. The work is detailed and ongoing: spec reviews, technical discussions, interoperability alignment. It's the part of the lifecycle most customers never see, but it directly shapes how quickly each new PCIe generation becomes usable.

Where this shows up clearly is in how PCIe moves from spec to deployment.

For PCIe 6.x, Synopsys IP was selected as the first PCIe 6.x Gold System for compliance testing. That provided the ecosystem with a complete working reference platform, well before commercial silicon was widely available, allowing companies to start validating designs earlier.

Synopsys has also:

• Demonstrated PCIe 6.x interoperability at 64 GT/s with multiple ecosystem partners, including dozens of industry firsts collaborations over several years
• Performed ongoing PCIe 7.0 interoperability and multi-partner validation at 128 GT/s, for electrical, optical, and protocol demonstrations
• Shown future-looking PCIe 8.0 electrical performance at 256 GT/s, pushing early readiness for the next generation
• Demonstrated viability of PCIe over optics with multiple partners, including a recent demonstration with 8-lanes at 64 GT/s

Bandwidth demand isn't slowing down—especially in AI and HPC systems.

PCIe 8.0 will push data rates to 256 GT/s, bringing new challenges in signaling, power, and system design. Work is already underway across PCI-SIG to define and validate those capabilities. See our latest link training protocol simulation with Paul Cassidy at the 2026 DevCon:

Synopsys IP for PCIe is built on the same engineering experience reflected in these contributions, spanning seven generations, from early specification work through silicon validation and broad ecosystem deployment.

That shows up in practice: in widely adopted and trusted complete IP solutions, including PHY, controller, security, and Verification IP. As PCIe continues to scale—from 64 GT/s to 128 GT/s and now toward 256 GT/s—the ability to move confidently from specification to working silicon becomes more critical with each generation.

Taken together, this is what sustained standards participation enables. It's not just expertise over where PCIe is going; it's the ability to help customers get there faster, with proven IP, early validation, and a clearer path to interoperability at scale. Every time your laptop boots from a PCIe SSD, or an AI agent runs on a PCIe system to accomplish some task for you, remember that Paul Cassidy and 50 other engineers from Synopsys had a part in making that work.