Advancing UCIe Performance: Enabling 40G for Next-Generation Multi-Die Designs

As multi-die designs continue to scale across AI and high-performance computing (HPC), the demand for higher bandwidth, tighter integration, and predictable system-level performance has never been greater. Designs are integrating more dies (also called chiplets) within a single package, driving the need for faster, more robust die-to-die connectivity.

The Universal Chiplet Interconnect Express (UCIe) standard was created to address this challenge, providing a common interface for interoperable, high-speed communication between chiplets. As adoption grows, the focus is shifting beyond interoperability to performance, scalability, and silicon-proven reliability.

Synopsys has achieved the industry's first UCIe-A silicon operating at 40G per lane, marking a significant milestone in advancing die-to-die connectivity.

This demonstration goes beyond isolated measurements. It showcases a complete UCIe-A link, including both transmit (TX) and receive (RX) paths, operating in mission mode across 64 lanes. The results include a wide-open RX eye at 40G, confirming strong signal integrity and system margin at these higher data rates.

The test chip is implemented in an advanced 3-nm process node and integrated using advanced packaging, reflecting real-world design conditions for leading-edge multi-die designs. Importantly, the demonstration leverages embedded DFT capabilities within the PHY, enabling RX-side eye recovery and providing critical visibility into in-system behavior.

For customers, milestones like this are not just about peak performance; they're about confidence.

As multi-die designs become more complex, design teams require:

• Silicon-proven IP to reduce integration risk
• High-bandwidth scalability to support growing workloads
• System-level observability to accelerate bring-up and debug

By validating full-link operation at 40G with strong margin and visibility, this achievement helps address all three.

The industry is transitioning from early chiplet adoption to large-scale deployment across AI, HPC, and beyond. In this phase, success depends not only on standards compliance, but on the ability to deliver predictable, scalable, and high-performance implementations.

Reliable 40G and 64G UCIe operation represents a critical step in that direction, enabling designers to push the boundaries of bandwidth while maintaining the robustness required for production systems.

Synopsys continues to invest in advancing UCIe IP and multi-die design solutions, helping customers accelerate innovation and bring next-generation systems to market faster.