Ethernet Standards for Scale-Up AI: An Overview of ESUN, SUE, and UALink

ESUN (Ethernet for Scale Up Networking) is an OCP workstream launched at OCP Global Summit 2025. It’s an open technical forum to advance Ethernet for the scaleup domain, focusing on how switches and NICs handle AI pod traffic: framing, lossless delivery, header optimization, and interoperability across vendors. ESUN explicitly coordinates with IEEE 802.3 and the Ultra Ethernet Consortium (UEC).

• Lossless, low latency behavior in single hop/multi-hop topologies: Defines L2/L3 behaviors and QoS mechanisms suitable for pods, where tail latency dominates job completion time.
• Header efficiency and switching pipelines: Encourages compact headers and switch features tuned for small payloads common in collectives.  
• Interop across vendors: Establishes a common baseline so XPU interfaces and Ethernet switch ASICs cooperate predictably in scale‑up deployments.

ESUN creates the standards coordination layer many operators want: open, vendor neutral L2/L3 behavior that they can implement on different switch silicon and NICs—without abandoning Ethernet. This complements endpoint/transport efforts (e.g., SUE-T in OCP and UEC profiles) and makes Ethernet the connective tissue for scaleup as well as scale out.

SUE (Scale Up Ethernet) is a framework specification contributed to OCP (v1.0 released Sept 5, 2025) that spells out how an Ethernet based pod should work. It introduces an AI Fabric Header (AFH) to minimize per packet overhead and defines Link Level Retry (LLR) and Credit Based Flow Control (CBFC) for hop-by-hop reliability with deterministic tail latency. 

• AI Fabric Header (AFH): A compressed header that carries only the fields scaleup needs (IDs, ordering hints, class), shrinking the header to payload ratio for the frequent 64byte units used in collectives.
• LLR (Link Level Retry): Buffers and retransmits frames at the link layer to mask errors from higher layers—reducing tail latency by avoiding costly end to end retries.
• CBFC (Credit Based Flow Control): Receiver advertised credits ensure the sender only transmits when buffer space exists, preventing drops with fine grained control compared to PFC (Priority-based Flow Control).
• Single hop pod topology: Encourages parallel planes to increase throughput while keeping latency bounded—exactly what heavily synchronized AI jobs demand. 

SUE’s LLR/CBFC mechanisms align with UEC’s Ethernet extensions, which document control ordered sets and preamble signaling for LLR/CBFC at the PHY/PCS boundary—evidence of cross community convergence on scale up reliability. 

SUE gives operators and silicon vendors a concrete “how to” for building Ethernet pods today. AFH reduces header overhead; LLR/CBFC deliver lossless, deterministic transport without heavyweight end to end retries; and the single hop model fits the core AI collective traffic shape.

UALink is a consortium standard enabling load/store/atomic operations directly between accelerators and switches—turning a pod into a shared memory domain. The UALink 200G 1.0 spec (publicly released April 2025) supports 200G per lane signaling, x1/x2/x4 link configurations, and scales to up to 1,024 accelerators per pod with deterministic performance.

• Four layer stack: Physical (leveraging standard Ethernet PHY components), Data Link (fixed FLITs + LLR/CRC), Transaction (compressed addressing), and Protocol (memory semantics).
• Switch ecosystem for accelerators: UALink Switches connect accelerators with ID based routing and support Virtual Pod partitioning and security (UALinkSec).
• Ecosystem alignment: Reuses Ethernet cables, connectors, retimers, and management—accelerating adoption while keeping BOM predictable.

OCP collaboration: OCP and UALink announced joint work to integrate UALink into community delivered AI clusters.

UALink provides memory semantics and TL/Protocol behaviors; ESUN/SUE address L2/L3 framing, reliability, and switch behavior. Many deployments will use UALink inside the pod and ESUN/SUE aligned Ethernet behaviors for interoperability and operations, with standard Ethernet for scale out between pods.

AI workloads increasingly rely on shared-memory programming models, which traditional Ethernet cannot efficiently support. UALink addresses this by enabling load/store and atomic operations across accelerators, making a pod behave like a unified memory domain. This reduces software complexity, improves performance for memory-intensive models, and scales to 1,024 accelerators per pod—all while leveraging standard Ethernet physical components for cost efficiency and ecosystem compatibility.

No matter which approach you choose—ESUN, SUE, or UALink—the physical layer (L1) is critical. It must deliver high signal integrity, margin, and jitter tolerance, with zero post-FEC BER across real-world channels. Synopsys 224G Ethernet PHY IP meets these demands enabling up to 1.6T Ethernet and supporting UALink 200G signaling, all while complying with evolving IEEE 802.3 and OIF-224G electrical specifications.

Open Ethernet is emerging as the foundation for scale-up AI networking. Together, ESUN, SUE, and UALink form a complementary stack: ESUN coordinates open Ethernet behaviors, SUE provides a pod-level blueprint with features like AFH and LLR/CBFC to reduce overhead and latency, and UALink introduces memory semantics for shared-memory workloads—scaling up to 1,024 accelerators per pod using Ethernet physical components. These efforts deliver lossless, deterministic performance without proprietary lock-in.

At the physical layer, high-speed Ethernet PHY technology enables all three approaches. Synopsys silicon-proven 224G PHY IP solution delivers the performance, interoperability, and robustness needed to accelerate deployment of open, multi-vendor scale-up fabrics—ensuring readiness for next-generation AI clusters.