World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects

AI clusters are getting bigger, faster, and hungrier. Training trillion-parameter models requires thousands of accelerators working in lockstep, and every nanosecond of interconnect latency and every milliwatt of interconnect power matters at scale. The problem? Traditional optical interconnects weren't built for this. They rely on retimers and digital signal processors (DSPs) inside the optical module to condition signals — components that add power, latency, heat, and cost to every single link in the system.

As data centers push toward 800G and 1.6T deployments, this overhead is becoming a serious bottleneck. Interconnects already contribute roughly 27% of total data center power, and that number has increased 46x since 2010. Something has to give.

The payoff is significant:

• Up to 50% power reduction compared to conventional retimed optical modules
• Lower latency — fewer processing stages means data moves faster between accelerators
• Reduced thermal burden — less power means less heat, which matters enormously in dense AI racks
• Simplified system design — fewer components, fewer failure points, more predictable behavior

But there's a catch. Without DSP-based signal conditioning in the module, the host PHY has to do all the heavy lifting. It needs to deliver exceptional signal integrity, robust equalization, and reliable data recovery across real-world channel conditions — all while meeting industry standards that ensure multi-vendor interoperability.

Before linear optics can scale across the industry, designers need confidence that the technology meets rigorous, standardized performance requirements. The OIF-CEI-112G-LINEAR-PAM4 specification by Optical Internetworking Forum (OIF) was created to provide exactly that — a common set of electrical limits, test points, and compliance methods for 112 Gb/s per-lane linear interfaces operating at 53 Gbaud PAM4.

This standard is critical because it transforms what could be a fragile, vendor-specific implementation into a repeatable, interoperable ecosystem. Without it, every host-module combination would require custom tuning and pairwise validation — a nightmare for deployment at hyperscale.

The question was: could a host PHY actually meet these requirements with real margin?

Synopsys has developed the industry's first 112G PHY IP fully compliant with the OIF-CEI-112G-LINEAR-PAM4 specification — and the results go well beyond basic compliance.

Our transmitter characterization confirms strong signal integrity under standardized test conditions. Key metrics — including voltage modulation amplitude (VMA), jitter, and eye closure — meet and in several cases exceed CEI-defined limits across multiple temperature conditions.

On the receive side, jitter tolerance (JTOL) measurements confirm the receiver can reliably recover data in the presence of injected sinusoidal jitter and real-world channel impairments. The results demonstrate resilience to timing variation and noise, meaning reduced bit errors, fewer retransmissions, and stable link operation under stressed conditions.  Link stability is a major concern for AI/ML networks.

Together, these results validate that the Synopsys 112G PHY meets — and in several cases exceeds — the OIF-CEI-112G-LINEAR-PAM4 specification, confirming its ability to support DSP-less host-to-module connectivity while maintaining signal integrity across the full link.

This isn't just a compliance checkbox. It's proof that linear host-to-module connectivity is now a viable, production-ready approach for next-generation AI and hyperscale systems.

By shifting complexity away from DSP-heavy optical modules and into the host, designers can reduce system power, latency, and thermal constraints — without compromising signal integrity. And because it's standards-based, this approach provides the multi-vendor interoperability that disaggregated AI infrastructures demand. 

The 112G PHY IP is part of a broader Synopsys ecosystem that includes MAC and PCS controllers, MACsec security, and verification IP — as well as Synopsys' complete HPC IP portfolio spanning PCIe 6.x/7.0, CXL, UALink, die-to-die, memory interfaces, and foundation IP. It's a complete interconnect solution for scaling AI from chip to system.

112G linear compliance is a milestone, not a destination. The OIF has already launched CEI-224G-Linear, extending DSP-less host-to-module signaling to 224 Gbps per lane. CEI-224G-LR/MR drafts are in member review, and two CEI-448G framework projects are now scoping the electrical interfaces for 3.2T and 6.4T links. The pattern is locked in: every future data rate will have a linear variant, and the PHY IP that meets those specs will sit at the center of every optical link.

That matters because co-packaged optics (CPO) — optical engines integrated directly alongside switch ASICs, eliminating the copper trace entirely — is entering production. CPO depends on the same principle 112G linear compliance validates: a host PHY that drives optics cleanly, no DSP in the path. As CPO moves from scale-out to scale-up fabrics, standards-compliant linear PHY IP is the bridge between compute silicon and photonics.

Linear optics, CPO, chiplets, standards-driven interop — these aren't parallel trends, they're converging into a single architecture. With the industry's first OIF-CEI-112G-LINEAR-PAM4 compliant PHY and an HPC IP portfolio spanning SerDes, PCIe, CXL, UCIe, and die-to-die interconnects, Synopsys is building that architecture now.

For the complete test methodology, transmitter and receiver characterization data, and detailed compliance analysis, download the whitepaper: Standards-Compliant 112G PHY for Linear Optics: Driving Efficient AI Infrastructure →