DesignWare PHY IP for PCI Express 3.1
The multi-channel DesignWare® PHY IP for PCI Express 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective solution that is designed to meet the needs of today’s high-speed chip-to-chip, board-to-board, and backplane interfaces while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies. The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity. This capability reduces both product development cycles and the need for costly field support. Synopsys offers a portfolio of silicon-proven IP for PCI Express consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard for PCI Express, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.
DesignWare IP for PCI Express Complete Solution Datasheet DesignWare PHY IP for PCI Express 3.1 Datasheet
Highlights
Products
Downloads and Documentation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
- Power gating and power island
- Embedded bit error rate (BER) tester and internal eye monitor
- Build-in Self Test vectors, PRBS generation and checker
- IEEE 1149. 6 AC JTAG Boundry Scan
- Supports -40C to 125C junctions
- Supports optional wirebond and flip-chip packaging
| 10G PHY for PCIe 3.0, TSMC 16FFC x2 for Automotive, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFC x4 for Automotive, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 10FF x1, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFC x16, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFC x1, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFC x2, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFPGL x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 10G PHY for PCIe 3.0, TSMC 16FFPLL x1, North/South (vertical) poly orientation | STARs | Subscribe |
| 8G PHY for PCIe 3.0, TSMC 28HPC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| 8G PHY for PCIe 3.0, TSMC 28HPM x1, North/South (vertical) poly orientation | STARs | Subscribe |
| 8G PHY for PCIe 3.0, TSMC 28HPM x2, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 3.0 PHY, GF 28HPP x4, East/West poly orientation | STARs | Subscribe |
| PCIe 3.0 PHY, GF 28HPP x8, East/West poly orientation | STARs | Subscribe |
| PCIe 3.0 PHY, TSMC 28HPC x4, North/South (vertical) poly orientation | STARs | Subscribe |
| PCIe 3.0 PHY, TSMC 28HPC x8, North/South (vertical) poly orientation | STARs | Subscribe |
| Description: | 10G PHY for PCIe 3.0, TSMC 10FF x1, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc10ffx1ns |
| Version: | 1.03a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_10FF_x1 |
| Product Code: | B942-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFC x1, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc16ffc_x1ns |
| Version: | 1.03b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_16FFC_x1 |
| Product Code: | B988-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFC x16, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc16ffc_x16ns |
| Version: | 1.04b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_16FFC_x16 |
| Product Code: | C420-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFC x2 for Automotive, North/South (vertical) poly orientation |
| Name: | dwc_ap_c10pcie3phy_tsmc16ffc_x2ns |
| Version: | 1.04b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | AP-PCIe-30-PHY_TSMC_16FFC_x2 |
| Product Code: | C085-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFC x2, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc16ffc_x2ns |
| Version: | 1.04b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_16FFC_x2 |
| Product Code: | C047-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFC x4 for Automotive, North/South (vertical) poly orientation |
| Name: | dwc_ap_c10pcie3phy_tsmc16ffc_x4ns |
| Version: | 1.04b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | Contact Us for More Information |
| Download: | AP-PCIe-30-PHY_TSMC_16FFC_x4 |
| Product Code: | C372-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFC x4, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc16ffc_x4ns |
| Version: | 1.04b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_16FFC_x4 |
| Product Code: | B943-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFPGL x4, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc16ffpgl_x4ns |
| Version: | 1.05a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_16FFPGL_x4 |
| Product Code: | A827-0 |
| Description: | 10G PHY for PCIe 3.0, TSMC 16FFPLL x1, North/South (vertical) poly orientation |
| Name: | dwc_c10pcie3phy_tsmc16ffpll_x1ns |
| Version: | 1.05bpatch1 |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C10_TSMC_16FFPLL_x1 |
| Product Code: | B865-0 |
| Description: | 8G PHY for PCIe 3.0, TSMC 28HPC x4, North/South (vertical) poly orientation |
| Name: | dwc_c8g_pcie3phy_tsmc28hpc_x4ns |
| Version: | 1.04d |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_TSMC_28HPC_x4 |
| Product Code: | A731-0 |
| Description: | 8G PHY for PCIe 3.0, TSMC 28HPM x1, North/South (vertical) poly orientation |
| Name: | dwc_c8g_pcie3phy_tsmc28hpm_x1ns |
| Version: | 1.04b |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C8_TSMC_28HPM_x1 |
| Product Code: | A767-0 |
| Description: | 8G PHY for PCIe 3.0, TSMC 28HPM x2, North/South (vertical) poly orientation |
| Name: | dwc_c8g_pcie3phy_tsmc28hpm_x2ns |
| Version: | 1.04a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_C8_TSMC_28HPM_x2 |
| Product Code: | A768-0 |
| Description: | PCIe 3.0 PHY, GF 28HPP x4, East/West poly orientation |
| Name: | dwc_pcie3phy_gf28hpp_x4ew |
| Version: | 1.08a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_GF_28HPP_x4EW |
| Product Code: | 9022-0 |
| Description: | PCIe 3.0 PHY, GF 28HPP x8, East/West poly orientation |
| Name: | dwc_pcie3phy_gf28hpp_x8ew |
| Version: | 1.08a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_GF_28HPP_x8EW |
| Product Code: | 9023-0 |
| Description: | PCIe 3.0 PHY, TSMC 28HPC x4, North/South (vertical) poly orientation |
| Name: | dwc_pcie3phy_tsmc28hpc_x4ns |
| Version: | 1.12a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_E10_TSMC_28HPC_x4 |
| Product Code: | B063-0 |
| Description: | PCIe 3.0 PHY, TSMC 28HPC x8, North/South (vertical) poly orientation |
| Name: | dwc_pcie3phy_tsmc28hpc_x8ns |
| Version: | 1.12a |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | PCIe-30-PHY_E10_TSMC_28HPC_x8 |
| Product Code: | B064-0 |
