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DesignWare PHY IP for PCI Express 3.1

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The multi-channel DesignWare PHY IP for PCI Express 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY is small in area and provides a low-power, cost-effective solution that is designed to support PCI-SIG PCIe 3.x, 2.x, and 1.x standards and to meet the needs of applications with high-speed chip-to-chip, board-to-board, and backplane interfaces. In addition, its low power consumption cuts both active and standby power for mobile SoCs.

Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies.

The DesignWare PHY IP for PCI Express 3.1 reduces both product development cycles and the need for costly field support by employing internal test features. The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity.

As the leading provider of PCI Express IP, Synopsys offers a complete PCI Express 3.1 IP solution, including digital controllers, PHY, and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 8.0 Gbps PCI Express interface into their high performance SoC designs.

You can view all Synopsys PCI Express videos here.

DesignWare IP for PCI Express Complete Solution Datasheet
DesignWare PHY IP for PCI Express 3.1 Datasheet
 

  • Supports all the required features of the PCI Express 3.x (8.0 GT/s), 2.x (5.0 GT/s) and 1.x (2.5 GT/s) specifications as well as the PHY interface for PCIe (PIPE) 3 and 4 (8-bit, 16-bit and 32-bit) specifications
  • Supports a wide range of PCI Express lane aggregation up to 16-lanes and full bifurcation
  • Includes robust backchannel initialization and advanced power management features including L1 sub-states in conjunction with power gating techniques
  • Exceeds electrical specifications in areas of margin and receive sensitivity for a robust design
  • Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
  • Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing
  • Industry's leading, complete PCI Express 3.1 IP solution: digital controllers, PHY and verification IP
  • Supports advanced 28-nm and 14/16-nm FinFET technologies and flip-chip packaging
8G PHY for PCIe 3.0, TSMC 28HPC x4, North/South (vertical) poly orientationSTARsSubscribe
8G PHY for PCIe 3.0, TSMC 28HPM x1, North/South (vertical) poly orientationSTARsSubscribe
8G PHY for PCIe 3.0, TSMC 28HPM x2, North/South (vertical) poly orientationSTARsSubscribe
PCIe 3.0 PHY, GF 28HPP x4, East/West poly orientationSTARsSubscribe
PCIe 3.0 PHY, GF 28HPP x8, East/West poly orientationSTARsSubscribe
PCIe 3.0 PHY, TSMC 28HPC x4, North/South (vertical) poly orientationSTARsSubscribe
PCIe 3.0 PHY, TSMC 28HPC x8, North/South (vertical) poly orientationSTARsSubscribe

  Description 8G PHY for PCIe 3.0, TSMC 28HPC x4, North/South (vertical) poly orientation
  Name dwc_c8g_pcie3phy_tsmc28hpc_x4ns
  Version 1.0a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download dwc_c8g_pcie3phy_tsmc28hpc_x4ns
  Product Code A731-0
  
  Description 8G PHY for PCIe 3.0, TSMC 28HPM x1, North/South (vertical) poly orientation
  Name dwc_c8g_pcie3phy_tsmc28hpm_x1ns
  Version 1.1a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download PCIe-30-PHY_C8_TSMC_28HPM_x1
  Product Code A767-0
  
  Description 8G PHY for PCIe 3.0, TSMC 28HPM x2, North/South (vertical) poly orientation
  Name dwc_c8g_pcie3phy_tsmc28hpm_x2ns
  Version 1.1a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download PCIe-30-PHY_C8_TSMC_28HPM_x2
  Product Code A768-0
  
  Description PCIe 3.0 PHY, GF 28HPP x4, East/West poly orientation
  Name dwc_pcie3phy_gf28hpp_x4ew
  Version 1.08a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download PCIe-30-PHY_GF_28HPP_x4EW
  Product Code 9022-0
  
  Description PCIe 3.0 PHY, GF 28HPP x8, East/West poly orientation
  Name dwc_pcie3phy_gf28hpp_x8ew
  Version 1.08a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download PCIe-30-PHY_GF_28HPP_x8EW
  Product Code 9023-0
  
  Description PCIe 3.0 PHY, TSMC 28HPC x4, North/South (vertical) poly orientation
  Name dwc_pcie3phy_tsmc28hpc_x4ns
  Version 1.11a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation Contact Us for More Information
  Download PCIe-30-PHY_E10_TSMC_28HPC_x4
  Product Code B063-0
  
  Description PCIe 3.0 PHY, TSMC 28HPC x8, North/South (vertical) poly orientation
  Name dwc_pcie3phy_tsmc28hpc_x8ns
  Version 1.11a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation Contact Us for More Information
  Download PCIe-30-PHY_E10_TSMC_28HPC_x8
  Product Code B064-0