2024-11-05 08:52:35
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.x meets
today’s demands for higher bandwidth and power efficiency across network
interface card (NIC), backplane, and chip-to-chip interfaces. The PHY’s unique
DSP algorithms optimize analog and digital equalization and the patent-pending
diagnostics features enable near zero link downtime. The PHY
minimizes package crosstalk, allows dense SoC integration for x16 links, and
achieves ultra low latency with an optimized data path that is based on an ADC
architecture. Support for multiple standards form factors including OCP 3.0,
U.2, and U.3 enable server and storage applications.
The Synopsys PHY IP for PCIe 6.x seamlessly interoperates with Synopsys
Controller IP for PCIe 6.x to provide a low-risk solution that designers can use
to accelerate time-to-market and efficiently deliver differentiated products that
require the 64GT/s PCIe 6.x and CXL 3.x technologies.
Synopsys PHY IP for PCI Express 6.0
Highlights
Products
Downloads and Documentation
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features
- Minimizes package crosstalk with placement-aware architecture
- Allows consistent performance across PVT variation with ADC/DSP-based architecture
- Supports PCIe Lane Margining at Receiver
- Supports L0p substate power state, power gating and power island
- Embedded bit error rate tester (BERT), non-destructive internal eye monitor, and first bit error rate (FBER)
- Built-in Self Test vectors, pseudo random bit sequencer (PRBS) generation and checker
- Supports -40°C to 125°C junction temperatures
- Supports flip-chip packaging
| PCIe 6.0 PHY G2 , TSMC N5 x2, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY NCS, TSMC N3E x4 1.2V, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY NCS, TSMC N3P x1 1.2V, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY NCS, TSMC N3P x4 1.2V, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, SS SF2 x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, SS SF4X x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation | STARs |
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| PCIe 6.0 PHY, TSMC N6 x4 1.2V, North/South (vertical) poly orientation | STARs |
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| Description: |
PCIe 6.0 PHY G2 , TSMC N5 x4, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_g2_tsmc5ff_x4ns |
| Version: |
2.50b |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC5FF Databook (PHY Version: 2.50b_d2) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC5FF Reference Manual (PHY Version: 2.50b_d2) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC 5FF Release Notes (PHY Version: 2.50b) ( TEXT )
|
| Download: |
dwc_pcie6phy_g2_tsmc5ff_x4ns |
| Product Code: |
H751-0 |
| Description: |
PCIe 6.0 PHY NCS, TSMC N3E x4 1.2V, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_ncs_tsmc3eff12_x4ns |
| Version: |
3.00a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC 3EFF Databook (PHY Version: 3.00a_d1) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC 3EFF Reference Manual (PHY Version: 3.00a_d1) ( PDF | HTML )
|
| Download: |
dwc_pcie6phy_ncs_tsmc3eff12_x4ns |
| Product Code: |
H921-0 |
| Description: |
PCIe 6.0 PHY NCS, TSMC N3P x1 1.2V, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_ncs_tsmc3pff12_x1ns |
| Version: |
3.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe6 PHY x1 for TSMC 3PFF Databook (PHY Version: 3.03a) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe6 PHY x1 for TSMC 3PFF Reference Manual (PHY Version: 3.03a) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe6 PHY x1 for TSMC 3PFF Release Notes (PHY Version: 3.03a) ( TEXT )
|
| Download: |
dwc_pcie6phy_ncs_tsmc3pff12_x1ns |
| Product Code: |
I560-0 |
| Description: |
PCIe 6.0 PHY NCS, TSMC N3P x4 1.2V, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_ncs_tsmc3pff12_x4ns |
| Version: |
3.03a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe6 PHY x4 for TSMC 3PFF Databook (PHY Version: 3.03a) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe6 PHY x4 for TSMC 3PFF Reference Manual (PHY Version: 3.03a) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe6 PHY x4 for TSMC 3PFF Release Notes (PHY Version: 3.03a) ( TEXT )
|
| Download: |
dwc_pcie6phy_ncs_tsmc3pff12_x4ns |
| Product Code: |
H921-0 |
| Description: |
PCIe 6.0 PHY, SS SF4X x4, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_sssf4x_x4ns |
| Version: |
2.00a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
DesignWare® Cores PCIe 6.0 PHY Firmware Application Note (Doc Version: 1.20a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databooks Synopsys PHY IP PCIe 6.0 PHY x4 for SS4LPP Databook (PHY Version: 2.00a) ( PDF | HTML )
Synopsys PHY IP PCS for the PCIe 6.0 PHY x4 for SS4LPP PHY/PCS Wrapper Databook (PCS Version: 1.70a, PHY Version: 2.00a) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe 6.0 PHY x4 for SS4LPP Reference Manual (PHY Version: 2.00a) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe 6.0 PHY x4 for SS4LPP Release Notes (PHY Version: 2.00a) ( TEXT )
|
| Download: |
dwc_pcie6phy_sssf4x_x4ns |
| Description: |
PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_sssf5a_x4ns |
| Version: |
1.01a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
DesignWare® Cores PCIe 6.0 PHY Firmware Application Note (Doc Version: 1.20a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook DesignWare® Cores PCIe 6.0 PHY x4 for SSSF5A Databook (PHY Version: 1.01a) ( PDF | HTML )
Reference Manual DesignWare Cores PCIe 6.0 PHY x4 for SSSF5A Reference Manual (PHY Version: 1.01a) ( PDF | HTML )
Release Notes DesignWare® Cores PCIe 6.0 PHY x4 for SSSF5A Release Notes (PHY Version: 1.01a) ( TEXT )
|
| Download: |
dwc_pcie6phy_sssf5a_x4ns |
| Product Code: |
H922-0 |
| Description: |
PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_tsmc5ff_x4ns |
| Version: |
1.09a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
DesignWare® Cores PCIe 6.0 PHY Firmware Application Note (Doc Version: 1.20a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC5FF Databook (PHY Version: 1.09a) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC5FF Reference Manual (PHY Version: 1.09a) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe 6.0 PHY x4 for TSMC5FF Release Notes (PHY Version: 1.09a) ( TEXT )
|
| Download: |
dwc_pcie6phy_tsmc5ff_x4ns |
| Description: |
PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_tsmc6ff12_x2ns |
| Version: |
3.00a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
DesignWare® Cores PCIe 6.0 PHY Firmware Application Note (Doc Version: 1.20a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe6 PHY x2 for TSMC 6FF Databook (PHY Version: 3.00a) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe6 PHY x2 for TSMC 6FF Reference Manual (PHY Version: 3.00a) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe6 PHY x2 for TSMC 6FF Release Notes (PHY Version: 3.00a) ( TEXT )
|
| Download: |
dwc_pcie6phy_tsmc6ff12_x2ns |
| Product Code: |
I336-0 |
| Description: |
PCIe 6.0 PHY, TSMC N6 x4 1.2V, North/South (vertical) poly orientation |
| Name: |
dwc_pcie6phy_tsmc6ff12_x4ns |
| Version: |
3.00a |
| ECCN: |
5E991/NLR |
| STARs: |
Open and/or Closed STARs |
| myDesignWare: |
Subscribe for Notifications |
| Product Type: |
DesignWare Cores |
| Documentation: |
Hide Documents...
Application Notes DesignWare® Cores PCIE6 PHY ATE Testbench Aplication Note (Doc Version: 1.01a) ( PDF | HTML )
DesignWare® Cores PCIe 6.0 PHY Firmware Application Note (Doc Version: 1.20a) ( PDF | HTML )
SerDes PCB and Packaging Design Guide (Doc Version: 2.60a) ( PDF | HTML )
Databook Synopsys PHY IP PCIe6 PHY x4 for TSMC 6FF Databook (PHY Version: 3.00a) ( PDF | HTML )
Reference Manual Synopsys PHY IP PCIe6 PHY x4 for TSMC 6FF Reference Manual (PHY Version: 3.00a) ( PDF | HTML )
Release Notes Synopsys PHY IP PCIe6 PHY x4 for TSMC 6FF Release Notes (PHY Version: 3.00a) ( TEXT )
|
| Download: |
dwc_pcie6phy_tsmc6ff12_x4ns |
| Product Code: |
G163-0 |
