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VC Z01X Fault Simulation
Comprehensive High-Speed Fault Simulation for Functional Safety Verification and Manufacturing Assurance
As the content of electronic systems in automobiles continues to grow, functional safety verification is emerging as an essential requirement in the verification of SoC and IP designs.
Synopsys VC Z01X fault simulation solution injects faults throughout automotive devices and simulates the effects to help users develop robust diagnostic tests and verify safety mechanisms to meet the fault injection requirements in the ISO 26262 automotive safety standard, and the IEC 61508 industrial safety standard.
Companies planning to target zero-defect and complement ATPG fault coverage by using fault simulation for their functional and BIST test patterns leading to reduced tester time. Synopsys VC Z01X fault simulation solution simulated faults not covered by ATPG solution and ensure that the current functional verification environment detects these faults leading to improved test coverage and be closer to achieving zero-defects.
VC Z01X Simulation Solution
Introduction
Built upon the industry leading fault simulator Z01X and the fastest functional simulator VCS, the key advantages of VC Z01X Functional Safety Verification solution are:
- Ease-of-use while transitioning from functional verification with VCS to fault simulation in VC Z01X by eliminating logic simulation mismatches
- Superior performance leveraging VCS optimizations
- Full SystemVerilog/UVM, C/C++ testbench stimulus support
- Integration with VC Formal FuSa in the Unified Fault Platform
VC Z01X key features:
- Versatile fault simulation: Combining the industry leading simulation performance with the proven concurrent fault engine allows simulation of the most advanced complex designs, like CPUs, GPUs, NPUs at both RTL and gate level
- Complete fault modeling for random hardware failure types defined in ISO 26262
- Fault Campaign Manager: Orchestrates the entire fault injection process with optimized fault simulation scheduling
- Static/Dynamic Testability Analysis
- Debug with Verdi Fault Analysis