VC Formal Videos

Nilabja Chattopadhyay, Design Verification Manager at Amazon, details how his primarily simulation-based verification team benefited from using VC Formal apps like FPV, SEQ, DPV, and FRV. This approach revolutionized their process and culminated in the impressive verification of FP16 in under 8 weeks.

Synopsys VC Formal DPV is not only used by leading companies designing CPU, GPU, AI/ML chips, it has also been used by Synopsys’ own Solutions Group to verify IP blocks and foundation cores since 2006. It is truly the golden standard of datapath verification tool in the industry.

Amber Telfer, Principal Engineer at Microsoft, discusses what formal performance indicators are and how they help management understand the progress made in your formal verification projects. Watch this video to learn how to use performance indicators to make your own formal work count.

Luv Sampat, Sr. Formal Verification Engineer at Qualcomm, discusses why it is important to reach 100% coverage closure and how Synopsys VC Formal’s FCA auto-scale technology has helped him solve coverage closure challenges.

Shaun Feng, Senior Principle Engineer at SiFive, explains what clock gating signoff means, why it is important, how designers can help, and whether RISC-V formal verification is different from other CPU formal verification methodologies.

VC Formal DPV, with HECTOR technology, has helped verification engineers find the toughest bugs in their datapath designs for over a decade. Learn about the history of HECTOR from Alfred Koelbl, Synopsys scientist, and architect of the technology.

Achutha KiranKumar V M, Intel Fellow, shares his insights on why formal adoption has accelerated in the last 5 years, why architectural verification is important in left shift project cycle, and how to build a formal team from the ground up.