Comprehensive Cell, I/O and Memory Characterization

SiliconSmart® is a comprehensive characterization solution for standard cells, I/O, complex cells and memory. It generates accurate model libraries tightly correlated with Synopsys’ digital implementation tools. Its built-in FineSim™ simulation technology and tight integration with the gold-standard HSPICE® circuit simulator enable characterization and signoff accuracy. SiliconSmart supports all of the standard models, including NLDM (non-linear delay model), CCS (composite current source) and AOCV (advanced on-chip variation) models. 


Accurate library characterization is the cornerstone of successful digital implementation. Synthesis, place-and-route, verification and signoff tools rely on detailed model libraries to accurately represent the timing, noise and power performance of digital and memory designs. The complexity of cell libraries dramatically increases as designs migrate to smaller process nodes. Process variability on these nodes requires fast characterization on hundreds of corners. Furthermore, foundries are constantly updating SPICE models, requiring repeated characterization runs. Low-power SoC design further complicates the characterization process by introducing complex cells such as multi-bit flip-flops, multivoltage level shifters and retention logic, which must be accurately characterized to ensure effective digital implementation across multiple power domains. 


Signoff-quality libraries with best correlation between HSPICE and PrimeTime® suite

  • SiliconSmart’s precise characterization and modeling capability combined with HSPICE golden accuracy is critical for producing signoff-quality library models, including timing, power, signal integrity and OCV to ensure best PrimeTime accuracy during static timing and power analysis. This unique platform-level integration of SiliconSmart produces the best correlation between PrimeTime and HSPICE for advanced technology nodes

Comprehensive solution

  • SiliconSmart is a comprehensive, unified solution that generates libraries for standard cells, I/Os and complex cells, such as multi-bit flip-flops and memories

High performance with pre-characterization optimization

  • SiliconSmart increases performance by using innovative pre-characterization optimization and intelligent optimization techniques that reduce the number of simulation runs required during the library characterization phase

Advanced node-ready

  • SiliconSmart is ready for characterizing and modeling libraries at advanced technology nodes, such as 16-nm and 14-nm. It supports generation of POCV coefficients and supports the latest FinFET models
Advanced cell characterization solutions

SiliconSmart, a single solution to characterize standard cells, complex cells, I/O and memory 

SiliconSmart Platform Integration

Platform-level integration of SiliconSmart with HSPICE and PrimeTime ensures signoff-quality libraries 

Superior Model Accuracy for Advanced Process Nodes

Standard cell libraries for 20-nm and below process technologies require extremely accurate timing and noise models to ensure confident static timing analysis signoff—especially for mobile IC applications operating at ultra-low voltages. Small inaccuracies in the timing or noise models can lead to significant inaccuracies in static timing and noise analysis because the chip operating voltage is often very close to the transistor switching voltage. This is a new phenomenon in advanced nodes that must be taken into account in both the characterization and static timing analysis solution. To meet the accuracy needs for advanced node characterization, SiliconSmart model generation has been tightly calibrated with PrimeTime and HSPICE for best correlation and accuracy.

Fast Characterization Across Multi-CPU, Multi-Machine Systems

SiliconSmart delivers high-throughput characterization speed with its built-in FineSim SPICE simulator and tight integration with HSPICE. SiliconSmart intelligently combines measurements into simulation arcs, optimizing the number of simulations and accelerating that process through parallel characterization. Its adaptive parallel job manager distributes simulations to a network of computer servers and automatically adjusts CPU loading based on CPU performance and the job queuing platform. Overall characterization throughput improvements are nearly linear with each additional CPU. The default configuration for SiliconSmart supports five CPUs, but the user can increase this count to as many CPUs and simulator licenses as are available. 

Automatic Function Recognition and Vector Generation

SiliconSmart reads in a CMOS transistor-level cell netlist and performs static structural analysis to automatically determine functionality. Based on Channel Connected Block (CCB) partitioning and logic cone tracing between primary outputs and inputs, this analysis handles a wide range of cells, from simple standard cells to retention logic and I/O cells. Circuit topology revealed by the automatic function recognition also allows SiliconSmart to generate a set of vectors to simulate all possible arcs for a cell. This automatically generated vector set covers all necessary stimuli without any redundancy and minimizes the number of simulations required to characterize a cell without any loss of arc coverage or model accuracy.

To enable characterization of only certain cell paths, SiliconSmart also supports the use of traditional user-defined functions, as well as input vectors to guide the cell initialization sequence and measurements for model creation.

Automatic function recognition and vector generation remove the dependency on a predefined function, such as that in an existing .lib file. This automation, combined with a rich set of supported features such as differential signals and variable electrical modes in a programmable cell, provide flexibility and ease-of-use in setting up a successful characterization run.

Pre-characterization and Constraint Acceleration Technology

SiliconSmart can further analyze the automatically generated vector set before final simulation. This precharacterization procedure includes sharing state-specific characterization conditions (also known as vector binning) and calling the built-in simulator to quickly grade these vectors in the bin. Controllable by a user-defined errortolerance level, the whole set of vectors can be categorized into different bins. Only one simulation is required for a single bin. Other vectors in the same bin can be represented by the same measurement results in the created models. This can significantly reduce overall characterization time.

SiliconSmart supports a wide range of constraint methodologies, from standard design flows to leading-edge performance applications for maximizing yield and performance. For example, SiliconSmart allows sampling of internal nodes in a sequential cell to look for glitches in order to remove potential optimism for setup/hold constraints. It also provides multiple ways of capturing the dependency between setup and hold checks for different design styles.

The SiliconSmart constraint acceleration technology shortens the traditionally time-consuming task of measuring constraints.

Process Variability Model Generation

SiliconSmart provides process variation modeling capability with support for advanced on-chip variation (AOCV) and parametric on-chip variation (POCV) models. POCV models are an efficient and compact method to model timing impact due to random process variations. POCV is emerging as a modeling methodology to better address over-design margining for 16-/14-nm process technologies. Synopsys is working with leaders in the semiconductor industry, including silicon foundries, semiconductor companies, IP providers, EDA tools companies and the IEEE-ISTO standards body, to enable this technology across the industry. 

Embedded Memory Recharacterization

A memory instance is generated by a memory compiler, which includes design netlist, physical layout, and electrical models. A memory compiler builds up its own database for modeling by simulating a very limited number of memory instances—usually a smallest, a largest and a few sizes in the middle.For a newly created instance that is not specifically contained in the memory compiler model database, the memory compiler uses interpolation and extrapolation to fit certain polynomial equations. It is inevitable that this approximation leads to inaccuracies in its models. SiliconSmart eliminates such inaccuracies by recharacterizing such instances accurately and quickly.

The SiliconSmart Memory solution delivers:

  • Accurate memory instance recharacterization using a 100% simulation-based approach
  • High throughput and capacity using the built-in FineSim Pro simulation technology
  • Effective stimulus-based netlist reduction to dynamically eliminate inactive portions of the memory netlist and speed up the simulation without compromising accuracy
  • Ease of setup using internal node identification and templates for memory function description
  • Recharacterization flexibility through simple vector generation and customization

Memory recharacterization applications:

  • Embedded SRAM
    • Synchronous/asynchronous
    • Single-port/dual-port
  • Embedded REG files
    • Single-port/dual-port
  • Embedded ROM

Library Validation

SiliconSmart includes a closed-loop library validation feature that compares cell functionality and data accuracy against a precharacterized golden library, ensuring model consistency between Liberty and Verilog formats. 

SiliconSmart Technology Features

  • Built-in FineSim SPICE simulator and tight integration with HSPICE
  • Parallel characterization distributed on heterogeneous compute farms with unlimited CPU counts
  • Supports industry-standard load sharing systems
    • LSF
  • Automatic library characterization setup
    • Automatic function recognition from SPICE netlist including state tablebased functions
    • Automatic circuit topology-driven vector generation
    • Automatic structure and/or simulation-based vector optimization (pre-char)
    • Automatic constraint acceleration technology for sequential measurements
    • Automatic characterization points and range selection
    • Automatic gathering of all data from simulation to create all model views concurrently
  • Active driver or emulated driver to supply realistic, non-linear input waveform shapes to characterization
  • State- and path-dependent timing and power
  • Dependency management via efficient simulation output caching
  • Automatic recharacterization flow using an existing .lib file
  • Tcl command-line user interface
  • Cell Types

  • Single- and multi-output combinatorial cells
  • Complex latches and flip-flops, including retention flops, multi-bit flops, dual-edge flops
  • Complex multi-voltage, bidirectional I/O cells
  • Tri-state and open-drain cells
  • Special cells including one-hot MUX, bus keeper and clock gating
  • Special I/O cells, including LVDS, USB, PGIO, DDR, PCI, SSTL
  • Inputs

  • SPICE transistor-level netlists
  • Differential inputs and outputs
  • Multiple voltage supplies
  • User-specifiable complex load networks
  • Characterization of multiple electric modes per driver
  • SiliconSmart Interface Formats

    SiliconSmart inputs and outputs


    • Liberty (.lib)
      • Non-linear delay model (NLDM)
      • Non-linear power model (NLPM)
      • CCS timing, power, noise, variationaware
      • Compact CCS
      • ECSM (version 2.1.1) timing, power, statistical (S-ECSM)
      • AOCV
      • POCV
    • Verilog
    • VHDL
    • IBIS I/O models


  • Intrinsic delay and output transition time
  • Effective input pin capacitance
  • Minimum pulse widths
  • Setup, hold, recovery, minimum period and removal times
  • Constraint edge control
    • Dependent or independent setup and hold
  • Constraint violation determination
    • Functional failure
    • Absolute, relative and user-defined delay or slew degradation
    • Output and internal node glitch checking
  • Leakage and internal (propagated and hidden) power
  • Statistical model measurements
  • IBIS 5.0 measurements
    • Current and voltage curves plus different launch delay
    • On-die termination (ODT)
    • Programmable driver strength
    • Optimal point selection for static IV curve generation
  • Validation Features

  • Liberty model comparison
  • Automatic Verilog functional and back-annotation validation
  • Supported SPICE Simulators

  • FineSim
  • Cadence Spectre
  • Mentor Graphics Eldo
  • Platform Support

  • Red Hat Linux
  • SUSE Linux
  • Load Sharing Systems: LSF, SUNGRID