SiliconSmart reads in a CMOS transistor-level cell netlist and performs static structural analysis to automatically determine functionality. Based on Channel Connected Block (CCB) partitioning and logic cone tracing between primary outputs and inputs, this analysis handles a wide range of cells, from simple standard cells to retention logic and I/O cells. Circuit topology revealed by the automatic function recognition also allows SiliconSmart to generate a set of vectors to simulate all possible arcs for a cell. This automatically generated vector set covers all necessary stimuli without any redundancy and minimizes the number of simulations required to characterize a cell without any loss of arc coverage or model accuracy.
To enable characterization of only certain cell paths, SiliconSmart also supports the use of traditional user-defined functions, as well as input vectors to guide the cell initialization sequence and measurements for model creation.
Automatic function recognition and vector generation remove the dependency on a predefined function, such as that in an existing .lib file. This automation, combined with a rich set of supported features such as differential signals and variable electrical modes in a programmable cell, provide flexibility and ease-of-use in setting up a successful characterization run.