So you want to conquer your next big chip design using an advanced node FinFET process? From high-performance computing to the mobile edge, where a web of AI- and ML-enabled interconnected things are serving up real-time answers on the fly, one thing is for certain: Getting your library characterization right will help you reach design signoff faster and reduce the possibility of a respin.
Advanced process 3D FinFET technology enables more transistors to be packed into less space than ever. In fact, TSMC anticipates that its next-generation 3nm N3 process will have up to 70% density gain and up to 15% speed improvement at the same power as the previous N5 generation. But in addition to this technology enabling the future, there are more prominent timing, noise, and power variations that come along with it. And with hundreds of process, voltage, and temperature (PVT) corners on tens of thousands of cores, the scale of that challenge is getting bigger all the time.
We are far from the days of simple lookup table (LUT)-based non-linear delay model/non-linear power model (NLDM/NLPM) modeling for library-cell timing, noise, and power management. So in this new era of complexity, how do you ensure rapid chip design success even while compute demand is rising and market windows are narrowing?
TSMC and Synopsys have recently collaborated to lower your barrier to entry on advanced process FinFET technologies. Together we are helping to ensure your design success with our latest library characterization innovations to meet the moment.