Is Your Voltage Drop Flow Obsolete? Leading Design Teams are Rethinking Dynamic Voltage Drop (DVD)

Unexpected sagging of the supply voltage is a serious and growing issue for high-performance, advanced semiconductor designs. In fact, power supply integrity (EM/IR) has become an unmanageable challenge with the methodologies used by most chip designers today.

This article will cover the reasons why it has risen to a first-order concern, the impact on manufactured silicon, and why it is almost impossible for traditional approaches to measure and fix it. We will then introduce a fundamentally new approach for breaking through the voltage drop bottleneck.

There are a couple of reasons why voltage drop (or, IR-drop) has gotten so much bigger at advanced nodes. The first reason is that new finFET and gate-all-around (GAA) transistor topologies place a lot of transistor channels in a very small area, which raises the supply current (I) through smaller, higher-resistance (R) wires. 

The second reason is that power and heat dissipation have become huge problems. The #1 most effective technique for lowering total power is to lower the supply voltage. That’s because CMOS switching power is proportional to the square of the supply voltage. This drives supply voltages to be as small as possible, especially for high-performance designs with high operating frequencies. But that leaves only razor thin margins for any voltage drop in the power distribution network (PDN), and any voltage drop margin directly reduces the chip’s speed and performance. 

The real-world symptoms of these challenges are that many leading customers have reported that their silicon has a 10% lower maximum operating frequency (Fmax) than their simulation tools predicted. They found the root-cause for this discrepancy to be IR drop ‘escapes’: unanticipated and undetected activity scenarios that cause a higher-than-expected voltage drop. To solve this persistent gap between what the signoff tools predict and what the silicon actually delivers, they need to overdesign - which increases power consumption - and teams are investing huge amounts of time and compute resources as they try to catch more voltage-escapes before tapeout.

We now need to look at why it is so difficult for today’s EDA tools and methodologies to catch all voltage drop violations. What has changed, beyond IR drops just getting higher? The key insight is that dynamic voltage drops have become absolutely dominant in determining the worst-case IR-drop. Indeed, today’s advanced node standard cells draw intense, short bursts of current drawn when they switch from low to high or high to low. It is difficult to bring this current through long, thin supply wires from electrically distant power pads. The result is a brief dip in the local supply voltage. And if multiple cells in the same area all switch at the same time, then the local voltage will drop significantly as the power distribution network struggles to deliver the necessary current through large parasitic resistances. This local voltage drop effect is exactly similar to your lights dimming when the air conditioner switches on. Dynamic voltage drop is now much more significant and is responsible for up to 80% of the total local voltage drop.

Now we have come to the crux of the voltage drop problem for EDA: In order to calculate the worst-case voltage drop, we need to identify the realistic worst-case combination of simultaneously switching cells. But that search space is so vast that it is impossible to check all possibilities. It’s easy to see that N neighboring cells have 2N possible switching combinations, and N is typically in the millions. Clearly, not all switching scenarios are relevant (e.g.: cells that are very far apart) or even possible (e.g.: logical correlations and timing window overlaps restrict the possibilities). Despite these filters, there still remain an uncountably vast number of realistic switching scenarios. The drops in Fmax in silicon that we discussed earlier are typically due to real switching cases that cause significant local voltage drop but were missed by the signoff methodology. This is called the “coverage” problem.

Current DVD coverage methodologies rely on providing a large set of activity vectors and asking the power integrity tool to perform a transient analysis (= SPICE simulation of entire power network) for each vector (a ‘vector’ is essentially a list of cells switching in the same clock cycle). These vectors typically come from simulations that, ideally, capture real circuit behavior. These are often complemented with vectorless analysis. “Vectorless” is a confusing misnomer and is identical to vectored analysis except that the activity vectors are generated automatically by the EDA tool (think ATPG). So, to the user it looks “vectorless” but, under the hood, it still relies on design activity.

While vectors are certainly useful to validate a set of known activity scenarios, they don’t provide good voltage drop coverage. Estimates put vector coverage in today’s flows at less than 10% of realistic switching scenarios. The answer might seem to just provide more vectors but that is not feasible because (a.) transient analysis for each vector is highly compute intensive which limits how many vectors can be analyzed in a realistic time, and (b.) even with many more vectors, the coverage would still remain low because the search space is so huge.

And that is where the industry is today – Despite investing huge amounts of compute resources to analyze power integrity, advanced node designers are left with low DVD coverage and still facing silicon escapes.

SigmaDVD is a powerful new technology that addresses the most urgent and difficult problem in power integrity signoff for advanced nodes. It provides much more comprehensive DVD coverage in less time and identifies root-causes with efficient shift-left techniques to avoid and fix voltage drop violations. Deploying SigmaDVD requires a methodology shift for chip designers and changes their existing signoff flows. Synopsys does not underestimate these challenges and has been collaborating closely for several years with leading customers to mature and prove out the technology and deploy it on real production designs. Synopsys believes this new SigmaDVD approach will become the standard methodology for DVD analysis in advanced node design flows.