A FinFET is a type of field-effect transistor (FET) that has a thin vertical fin instead of being completely planar. The gate is fully “wrapped” around the channel on three sides formed between the source and the drain. The greater surface area created between the gate and channel provides better control of the electric state and reduces leakage compared to planar FETs. Using FinFETs, results in much better electrostatic control of the channel and thus better electrical characteristics than planar FETs.

FinFETs are the basis for modern nanoelectronic semiconductor device fabrication. Microchips utilizing FinFETs became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm, 10 nm and 7 nm process nodes. It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one, to increase drive strength and performance.

FinFET Diagram 1 | Synopsys

Figure 1: Planar FET

FinFET Diagram 2 | Synopsys

Figure 2: FinFET

What are the design challenges with FinFETs?

Advanced geometry nodes such as FinFET pose significant design and manufacturing challenges that impact some implementation tools. In particular, complex multi-patterning lithography requirements involve:

  • Rule-aware placement and routing to ensure the ability to color masks correctly and efficiently
  • In-design physical verification throughout the flow to reduce time-consuming, uncertain iterations
  • Accurate higher levels of extraction and timing analysis to allow for manufacturing variability

Advanced geometry nodes will enable designs to run at multi-GHz+ operating frequency. In order to achieve this, improved modeling, guidance, and analysis should be handled by tools with high degrees of predictability throughout the design flow. Size and performance requirements for next-generation designs require higher levels of capacity, enhanced multi-core processing for faster runtime, and an integrated design environment to maximize design productivity. Synopsys’ comprehensive, foundry-certified advanced geometry solution provides the following features that help designs make it to market faster:​

  • Early RTL design exploration and block feasibility analysis​
  • Physical guidance from synthesis to place and route​
  • Digital and custom co-design for advanced mixed-signal requirements​
  • In-design physical verification with automatic detection and repair of complex design rules​
  • Tightly coupled extraction and signoff capabilities with implementation tools​
  • Physical ECO guidance and leakage recovery capabilities from signoff analysis

Benefits of Synopsys for FinFET SoC design

Taking advantage of the electrical characteristics of FinFETs requires addressing the challenges of complex, multi-patterning lithography. To help, Synopsys provides the industry's broadest silicon-proven FinFET-ready EDA solution spanning process development, SPICE design implementation, and IP. Other benefits of working with Synopsys for FinFET designs include:​

  • Our early collaboration with foundries and academia for the development of the latest models, process development, and certification​
  • Comprehensive solution addressing new challenges, such as double patterning and 3D transistors, introduced by 20nm planar and 16/14nm and below FinFET manufacturing rules with 3DIC integration​
  • Minimal impact on existing methodology with transparent adoption, easing the transition to advanced process technologies​
  • Complete foundry-certified solutions for IC design, implementation, and signoff for first-time-right silicon

How to enable volume-production FinFET designs

Synopsys has a proven track record for delivering the leading solutions targeting the most advanced process nodes. In collaboration with IDMs, foundries, and academia, Synopsys delivers the industry’s most comprehensive and effective FinFET solutions. Most of the world’s FinFET devices are designed with Synopsys’ TCAD tools; Synopsys has the broadest portfolio of silicon-proven IP for FinFET; and more than 90% of the leading volume-production SoCs have been designed with the Synopsys Design Family.

Synopsys’ Custom Compiler visually-assisted custom layout solution is tuned for rapid implementation, shortening the time required to complete FinFET custom design tasks from days to hours.

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