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The era of the monolithic die is over.
The next decade belongs to systems assembled from many specialized dies — 2.5D and 3D configurations that blend logic, memory, and accelerators on a single advanced package.
This is not just a new packaging trick. It’s a deeper contract between design and manufacturing. It’s an expanded model for verification. And it’s a growing mandate for AI: be fast, be useful, be explainable, and be right.
I see this shift every day.
Organic interposers with dozens of embedded bridges are becoming more commonplace, carrying dense interconnects between systems-on-chip (SoCs) and towering high-bandwidth memory (HBM) stacks. We pull power from the bottom of these structures and deliver it with precision to the hungriest blocks at the top. Heat is no longer an afterthought, but a design parameter that competes with timing and signal integrity.
When you assemble heterogeneous dies into one system, every assumption made in the “old world” of single-die design becomes a hypothesis that must be tested continuously, not a box checked at the end.
That’s why collaboration can no longer be a polite handoff. It must be a shared source of truth — from early architecture exploration to manufacturing and test — co-owned by design teams and foundries.
Depending on the application, the center of gravity may shift. Silicon-first for one program, packaging-first for another. But the principle is constant: manufacturing constraints must shape the earliest design decisions, not veto the last ones.
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Leaning on STCO and AI
We’ve talked for years about Design Technology Co-Optimization (DTCO). The future is now with System Technology Co-Optimization (STCO), which expands the focus on circuitry to encompass architecture, packaging, interconnects, and software. But it must be executable.
Picture an environment where node selection, metal stacks, interposer materials, bridge counts, and thermal strategies are not debates in meetings but parameters in a living model. Change the model, rerun the system, and watch the performance-power-thermal-reliability dynamics shift. This allows decisions to be backed by correlated signoff metrics, not just intuition or back-of-the-envelope calculations.
In this world, the EDA flow is constantly measuring, correcting, and converging.
Verification, accordingly, must evolve from a phase to a fabric woven through the flow. The early, assumption-driven shortcuts that once sufficed are now liabilities. Multi-die design requires package-aware timing, power integrity across multiple media, thermal coupling across stacks, and mechanical stress that evolves under workloads.
The only scalable approach is continuous verification that correlates early planning assumptions with late-stage realities. This is the key to ensuring what we greenlight at the architectural phase still holds true at signoff and in silicon.
And then there’s AI.
AI can already accelerate human learning, compressing the time it takes a packaging expert, a silicon designer, or a power integrity engineer to navigate unfamiliar tools and concepts. Agentic workflows can encode best practices, triage issues, and guide complex tasks. This is not about replacing engineers. It’s about removing the friction that keeps them from working at their highest level and giving them hundreds of virtual AgentEngineers™ to work with. But, make no mistake, the designers are still in charge.
A confident wrong answer wastes time at best and compromises silicon at worst. The standard for AI here is neither novelty nor speed — it’s verifiability. That means recommendations are traceable to the rules and models that govern signoff. It means explanations that engineers can inspect, audit, and improve. It means AI that is grounded in mature flows, rich documentation, and decades of edge cases.
The AI we adopt must be explainable, not just persuasive.
Addressing the physics of multi-die design
When put together, these interrelated trends bring the future of design into clearer view. Here’s where I believe we’re headed:
- Executable STCO will replace static planning. System architects, physical designers, and foundries will interact through shared, parameterized models. Changing a metal stack or bridge topology will be an experiment, not a negotiation.
- Verification will become telemetry. Package-aware checks will stream throughout implementation, creating a continuous loop that aligns early intent with late-stage proof, shortening cycles as a result.
- Design provenance will matter. We will track how a design decision was made, which data supported it, and how it survived verification. This provenance will become a key part of signoff, especially for AI-generated or AI-assisted steps.
- Agentic AI will scale people, not replace them. The winning deployments will be copilots or agents that steer engineers through multi-domain complexity, surface tradeoffs, and automate tedious tasks. And they will always be capable of showing and validating their work.
- Simulation will span the stack. From wafer to interposer to package to board to rack, we will simulate and correlate behavior, enabling decisions that reflect the real thermal, power, and reliability contours of the system in the field.
We are headed in these directions (quickly!) because the physics of multi-die designs demand it. As dies proliferate and interconnects grow denser, our margin for assumption shrinks.
EDA’s north star remains the same — predict with high confidence and precision how a design will behave in the real world — but the route has changed. We get there by treating collaboration as shared intelligence, verification as a continuous service, and AI as a trustworthy accelerator anchored to proven flows.
The teams that internalize these changes will ship more capable systems faster and with fewer surprises. The rest will keep adding people and time to a problem that requires neither — only a different operating model.
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