PrimePower RTL power estimation leverages the Predictive Engine from Synopsys' RTL Architect™ product to provide RTL designers with fast, scalable, and accurate power estimation for early analysis of RTL blocks, subsystems, and full-SoCs. PrimePower RTL enables designers to analyze, explore, and optimize their RTL with confidence, improving power, energy efficiency, and shortening the design cycle.
During implementation and signoff, PrimePower provides accurate gate-level power analysis reports for SoC designers to make timely design optimizations and achieve power targets. Supported power analysis includes average power, peak power, glitch power, clock network power, dynamic and leakage power, and multi-voltage power; with activity from RTL and gate-level vectors from simulation, emulation, and vectorless analysis. By closely integrating with PrimeTime, the golden industry standard for timing and signal integrity analysis and signoff, PrimePower expands the PrimeTime solution to deliver accurate dynamic and leakage power analysis and signoff for gate-level designs.