Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final signoff. SoC designers will gain the insights they need to:
- Identify which nets have glitches and how many
- Filter data to understand and rank the severity based on glitch duration and power consumption
- Remove glitches, recover power, and identify the critical windows for hand-off to glitch-aware implementation, ECO, and IR drop analysis
Patrick Sheridan, PrimePower Product Marketing
Ashwin Sudhakaramenon, PrimePower Application Engineer
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