The most critical component for dynamic power analysis and optimization is the quality of the vectors. Vector quality is defined by the realistic activity seen when the SoC is working in a real system. As mentioned above, the traditional power analysis process involved checking with the SoC architect to identify which vectors to use for power analysis and optimization. This was a hit or miss activity that didn’t always cover all aspects and scenarios.
To be able to accurately predict the amount of power that SoCs are going to consume, designers need to put them under a test bench that is a true-to-life representation of how they are going to be used. The best system that can be used to run live applications is called emulation.
The sheer amount of data involved in running a power analysis for an AI chip requires high-powered tools. Even when running an application for a few seconds on an emulator, the resulting data is massive (hundreds of gigabytes comprised of trillions or billions of clock cycles). To help solve this problem, power profiling within an emulation system identifies the window of interest for power analysis and prunes the windows from billions to millions to thousands which makes the power analysis from an emulation system much more practical.
Synopsys’ ZeBu Server is the industry’s fastest emulation system, delivering two times the performance of legacy emulation solutions by taking advantage of its unique Fast Emulation architecture, the most advanced commercial FPGAs, and innovations in FPGA-based emulation software. These software innovations enable users with faster compile, advanced debug, including native integration with Verdi, simulation acceleration, hybrid emulation, and, of course, power analysis.
Additionally, the new third dimension that comes into the picture when designing AI chips that isn’t as much of a factor in mobile chip design is temperature. Generating a heat map at an early stage via emulation becomes a lot more important for the entire design process.
When it comes to low power design for AI chips, adopting new methodologies and even new tools, like emulation, is critical to creating a tightly interwoven team of design professionals from many different disciplines.