Accelerate AI Design from Silicon to Systems: Building for the Physical AI Era

AI has officially extended beyond the data center. It's now in the cars we drive, the factories we run, the wearables we use to monitor our health, and the humanoid and service robots that are starting to share floor space with people. This is the era of physical AI: AI-powered systems that perceive, decide, and act in the real world.

It's one of the most exciting shifts the semiconductor industry has ever seen. It's also one of the hardest engineering problems we've ever taken on.

The AI market is now distributed across two reinforcing domains. Cloud AI trains models and performs large-scale inference. Edge AI deploys the models on‑device, enabling low latency, real‑time response, on‑device privacy, and graceful operation when disconnected from the cloud. As part of the edge, physical AI embodies the models, putting intelligence into machines and systems that interact with the real world through sensing, computation, and action, adding a physical aspect to the edge AI domain.

Each domain reinforces the other, and together they're reshaping the entire silicon value chain. Edge and physical AI products alone are projected to grow at roughly 35% CAGR through 2035 (Grandview, Cervi, Acumen Research, SNS Insider), driven by advances in sensing, the rise of humanoid and collaborative robots, automation in manufacturing and logistics, and the proliferation of on‑device AI.

The conclusion for anyone building silicon: the chip is no longer the product; the system is.

The hard part isn't the AI. It's the constraints around it.

Anyone shipping an intelligent device knows the uncomfortable truth: the breakthroughs in models, compute, memory, and sensors are exciting, but they're not what makes the project hard. The hard part is everything wrapped around the AI.

Designers are being asked to balance constraints that used to live in different conversations, all at the same time:

• Deterministic, real‑time behavior for perception, planning, and control in dynamic environments. Milliseconds matter, and "usually fast enough" isn't good enough.
• Heterogeneous compute efficiency, supporting everything from motor control to neural inference on strict performance‑per‑watt budgets.
• Functional safety (Automotive Safety Integrity Levels B to D and equivalents), requiring robust designs that deliver deterministic behavior and help prevent incorrect decisions with physical consequences.
• Cost and power discipline, because these are consumer volume markets and products must meet strict battery-life and charging requirements.
• Time‑to‑market pressure that is fundamentally out of sync with silicon cycles. New AI models appear every few months. Silicon still takes quarters. If you wait to see the product before you start the underlying design, you've already missed the market. 

Put it all together and one conclusion is unavoidable: this is a systems‑level engineering problem, not a single‑point optimization. Winning means getting an entire system-on-chip (SoC) and the system it lives in right the first time, on the right process, at the right cost. 

The catch is that no single layer of the design can deliver all of that on its own. The process has to be engineered for these realities at volume. The IP on top of it has to be broad enough to cover the building blocks a modern AI SoC actually needs and validated against that process with the same assumptions the SoC team will use at signoff. When those two layers are shaped around each other upstream, the foundation a customer inherits is genuinely ready. When they aren't, the gaps show up exactly where the project can least afford them.

Solving a systems problem requires a foundation that was built as a system: process technology, silicon IP, and design methodology that move together rather than meeting at the end.

This is the work Synopsys has been investing in: a broad, silicon‑proven IP portfolio spanning the building blocks modern AI SoCs depend on, high‑speed interfaces (PCIe, USB, MIPI, LPDDR, UCIe, HDMI/DP, UFS, D2D and more), foundation IP (embedded memories, logic libraries, I/Os, NVM), and silicon lifecycle management (PVT sensors, voltage monitors, thermal diodes), all engineered to support the deterministic performance, functional safety, low power, and cost discipline these designs demand. 

And because process matters as much as IP, Synopsys has enabled a portfolio using TSMC's -compact node platforms N6C (also known as N6 V1.1) and N4C. These compact nodes are proven, cost-optimized variants of N6 and N4P and bring the right balance of power, performance, features, and economics to high-volume AI designs. Purpose built for the realities of applications like edge and physical AI, they preserve the performance, power, and predictability of well-established platforms while enabling the economics these markets demand. 

The point isn't only the node or the IP list. The point is that the foundational layers are ready, predictable, and aligned with each other, so customer engineering teams can spend their creativity where it differentiates the end product: the AI capability, the application, and the user experience.

Every major shift in computing has been defined less by one breakthrough and more by how quickly an ecosystem learned to build around it. The PC era wasn't won by the CPU alone. The mobile era wasn't won by the application processor or modem alone. The cloud era wasn't won by the GPU alone.

Physical AI will be the same. The models will keep transforming and getting better. The sensor technology will keep getting smarter. But what will decide who ships, who scales, and who shapes the next decade is the work of co‑optimizing across process, IP, design, and systems so that ambitious ideas become manufacturable products.

That's the work in front of all of us. And it's a very good time to invest in building the future of silicon and systems.