SLM delivers multiple benefits to the chip designer and the end user of that chip. These include enhanced chip performance, smoother and faster product bring-up and enhanced performance and security over the life of the chip. Specific benefits include:
Improved Design Performance
Silicon data extracted during manufacturing test is used to calibrate design modeling parameters. Data from ring oscillator measurements, critical path test results and process/voltage/temperature (PVT) monitors are all example sources of this data.
Through a series of data mining, correlation and root cause analysis, the robustness and accuracy of the models used in chip design is improved. This allows initial chip design to converge on an optimal result faster.
Faster Product Yield Ramp and Improved Final Yield
This process correlates silicon data with physical design data to identify systematic yield limiting issues. The sources of the silicon data include test failure diagnostic data, process/voltage/temperature (PVT) sensor data and structural data.
Through a series of data mining, correlation and root cause analysis steps dominant yield loss mechanisms can be identified. This allows acceleration of the “yield learning” process to optimize the final product yield.
Test Time Reduction and Improved Product Quality
This process adapts test and screening criteria through ongoing analysis of silicon and manufacturing test result data. Optimized test criteria will reduce test time and ensure only good devices are released to production.
Sources of this data include manufacturing test results, process/voltage/temperature (PVT) sensor data and structural monitor data. Through a process of data mining, monitoring/analysis and reporting, adaptive test alerts and enhanced control measures can be implemented. The ability to detect outliers, or chips that exhibit performance outside of normal limits, is also enhanced.
The result is reduced test time and improved quality of the delivered chip.
Faster Time-to-Market for Chips and Systems
In any complex chip, there are interactions between hierarchical interconnects, heterogeneous processors, various operating systems and bare metal software. All these interactions must be harmonized in order get the chip and the system that uses it to market. Adding to this challenge is the fact that most systems are designed without really knowing what the workload will look like when the final system is deployed.
SLM can address these challenges through deep insight into the functionality of the compute, communication and storage resources on a chip. The combination of functional and structural monitors embedded in the chip, together with analysis software enable much faster and deeper understanding of the behavior of the chip’s operation and how it interacts with the overall system. In addition, during the life of the system, workloads change, software and firmware requirements change and transistors age. SLM also provides insights to allow the chip and system to adapt to these changes. The result is shorter development time, improved validation efficiency and better long-term performance.
Performance, Power, Reliability and Security Optimized Throughout Operational Life
The performance of a silicon chip does not remain constant over its operating life. Aging effects in the silicon structures change the performance characteristics of the device over time. The system operating environment can also contribute to changes in chip performance. These effects include environmental temperature effects and the impact of changes in workload and electrical operating parameters. Security breaches can also impact chip performance.
Semiconductor devices are performing more mission critical and safety-related functions in systems today. This makes the robustness and reliability of these devices more important. Many of these systems have a long operating life, and time also contributes to the gradual change in performance of semiconductor devices.
SLM provides a data collection, analysis and control environment to monitor all of these effects and implement corrective actions in the field at a unit device level. The result is far more stable and secure performance of the silicon device and overall system over time.
