HSAT IP generates an on-chip interface between the existing high-speed interface IO (i.e., USB, PCIe, etc.) and the DFT logic, which is typically composed of scan and compression logic. To accommodate this and remain independent of the HSIO, the HSAT IP logic interface utilizes the Arm® AMBA® AXI interconnect serving as a subordinate to the HSIO. The data feeds from the AXI through a FIFO that accommodates the packet length suitable for the design’s DFT. The HSAT IP interface also contains logic to transform the data packet to/from DFT signals, including scan in data, scan out data, scan enable, and test clock.
TestMAX ALE provides the software interface to the HSIO similar to a software device driver. TestMAX ALE enables communication between the operating system file I/O and the software layer driving the host HSIO. TestMAX ALE processes standard scan data in the IEEE 1450 (STIL) format and then packetizes the data for communication to the HSIO. Several output formats (ex. STDF-v2007) are supported to avoid further processing by external programs utilizing data.