Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
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Comprehensive, Advanced Design-for-Test (DFT)
Synopsys TestMAX DFT is a comprehensive, advanced design-for-test (DFT) tool that addresses the cost challenges of testing designs across a range of complexities. TestMAX DFT supports all essential DFT, including boundary scan, scan chains, core wrapping, test points, and compression. These DFT structures are implemented through TestMAX Manager for early validation of the corresponding register transfer level (RTL), or with Synopsys synthesis tools to generate netlists.
Multiple codecs and architectures are supported that address the need for ever-higher levels of test data volume, test time reduction, and fewer test pins. TestMAX DFT leverages Synopsys Fusion Technology to optimize power, performance and area for the design, minimizing the impact from DFT.
TestMAX DFT also leverages both IEEE 1500 and IEEE 1687 standards to provide a flexible test access infrastructure that is used to automate test integration and validation for testing system-on-chips (SoCs). This allows the integration and verification of IJTAG network, IJTAG-compliant hardware and the IEEE 1500 access network. The tool also enables ICL extraction and verification as well as hierarchical PDL pattern porting. Automated pattern porting and generation of tester-ready patterns in STIL/SVF/WGL and post-silicon failure diagnostics can also be achieved with TestMAX DFT.
Benefits
- Lowers test costs
- Enables high defect coverage
- Accelerates DFT validation using RTL
- Minimizes impact on design power, performance, and area
- Preserves low-power design intent
- Minimizes power consumption during test
- Integration and verification of IEEE 1687 network and compliant IP
- Integration and verification of IEEE 1500 access network
Features
- High test time and test data reduction
- Patented, powerful compression technologies
- RTL generation with TestMAX Manager
- Fused into Design Compiler® and Fusion Compiler™ for concurrent optimization of area, power, timing, physical and test constraints
- Hierarchical scan synthesis flow support
- Pin-limited test optimizations
- Unknown logic value (X) handling
- Location-aware scan chain reordering during incremental compile
- Core wrapping with shared use of existing core registers near core I/Os
- Analysis-driven test point insertion using TestMAX Advisor
- Flexible scan channel configurations to support multi-site testing and wafer-level burn-in
- Multiple compression configurations to support different testers and packages with different I/O
- Boundary scan synthesis, 1149.1/6 compliance checking and BSDL generation
- Consistent, comprehensive DRC shared with ATPG
- Enables TestMAX ATPG for compressed pattern generation
- IEEE 1687 ICL creation and verification
- Hierarchical IEEE 1687 PDL pattern porting
- Automated pattern porting and generation of tester-ready patterns in STIL/SVF/WGL and post-silicon failure diagnostics