Mastering AI Chip Complexity
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Address Testability Issues Early
Synopsys TestMAX Advisor, performs RTL testability analysis and optimization, allowing users to fine-tune RTL early in the design cycle to predictably meet manufacturing and in-system test coverage goals. Advisor is commonly used throughout the design implementation flow at various handoff points when the designs content changes.
Advisor checks for testability issues in advance, checking how suitable the RTL or netList is for test and checks to see if it is ready for DFT logic insertion. Advisor also performs analysis to determine where to place these DFT structures called test points that can improve the results of ATPG or Logic BIST.
Advisor is built on Synopsys SpyGlass® technology and provides a comprehensive set of early RTL testability analysis capabilities as well as allows the traditional netlist-based flow.
Figure 1: A complete solution for testability analysis
Benefits
- Shorten test implementation time and cost by ensuring RTL or netlist is scan-compliant
- Improve test quality by diagnosing DFT issues early at RTL or netlist
- Detects source of static and dynamic X Capture and provides impact analysis
- Reduce ATPG pattern counts and run times and improve coverage
- Systematically check DFT connections
Features
- DFT violation checking
- ATPG coverage estimation
- Test Robustness & Glitch Monitoring
- Test Points Selection
- Connectivity Validation