High-Speed Access & Test

High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle

Within the SiliconMAX Platform, High-Speed Access & Test (HSAT) IP plays a critical role enabling high-speed interfaces such as PCIe and USB, typically already present in SoCs, to be re-used for high-bandwidth production test. Further, this opens up the possibility to reuse the same high speed test packets and to repeat manufacturing tests in-system or in-field, providing visibility of functional or performance degradation during the device’s lifetime. 

FLow diagram of TestMAX ALE and SLT diagram

Fig 1. SiliconMAX High-Speed Access & Test IP + Synopsys TestMAX ALE Solution

When HSAT IP is combined with Synopsys TestMAX ALE software, standard high speed IO interfaces such as PCIe and USB can be re-used to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoid the need for large numbers of test and interface pins. Test time can be reduced because the link between the test time and GPIO data rate is eliminated. The solution can also be used to access to data from PVT and functional monitors at high speed.

Image of TestMAX ALE and SLT Flow Diagram

Fig. 2 Manufacturing tests can be repeated in-system and/or in-field.

Key Features

  • PCIe, USB functional protocol-based high-speed I/O for ATE, in-system & in-field
  • Other interfaces (e.g. SPI) for in-system/in-field available
  • Configurable Arm® AMBA® AXI slave interface to HSIO
  • Configurable scan chains (512 max) and TAP supported
  • Full RTL configuration and integration flow or Synopsys TestMAX Manager
  • Arm AMBA AXI testbench generation
  • Optional EBC interface for USB
  • Bypass mode allows scan chains to connect to HS Access & Test IP or GPIO pins
  • Multiple levels of loop back for link validation

Key Benefits

  • Easily repeat manufacturing tests in-system and in-field
  • Reduce test time by eliminating the constraint of GPIO test pin data rate
  • Re-use functional HSIO ports (PCIe and USB) for test and other data
  • Avoid the need for large numbers of GPIO test pins
  • High speed access to PVT & functional monitors and other sensor data
  • Bandwidth scales with each new generation of PCIe/USB

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