Assuming an example where the system has been specified, system simulations have been performed, microarchitecture is completed, low power choices for technology node, IP, etc., have been made, and coding of RTL and UPF are done. Given this, there are five main phases for low power design and verification methodology to be used to design the IC.
Static Power Verification and Exploration
In static verification, the first step is to ensure the inputs to the design flow (RTL, UPF, and SDC) are structurally and syntactically correct. By definition, static verification doesn’t use test vectors, so this is a very efficient way to review inputs before going into simulation or implementation flows. Lint and CDC checks are important in general to ensure your RTL is clean. UPF checks can be done either independently or with the corresponding RTL to ensure they are clean and SDC can also be statically checked along with RTL as well. In power exploration, early estimates for power for the RTL can be driven, either with estimated switching or actual waveforms from simulation. Choices can be made early on to improve the overall architecture of the design by performing early RTL power analysis.
Dynamic Power Verification and Analysis
In dynamic power verification, there are several important aspects to check. First off, does the sequence for the PMU control signals work correctly to shut down, clamp for isolation, save, restore, remove isolation clamp, and power up. This is an extremely important check with the design RTL and UPF together to make sure the design is functioning properly. Next, what type of waveforms and toggle activity are seen in the design? This will determine the dynamic power used since it depends on activity factor. The higher the activity factor, the more power is being used. Hence, the waveforms produced are very important to accurately estimate power both early and late in the process.
Software Driven Power Analysis
For emulation-based low power flows, it’s important to be able to capture the right peak windows for the design’s power profile. Emulation allows review of a much wider set of data, enabling one to choose
the windows that would be most valuable to generate waveforms to estimate power.
RTL-based predictive power estimation, logical synthesis, DFT insertion and physical implementation all have important low power specific roles to play. RTL-based predictive power estimation allows, very early on, to make RTL modifications with early power estimates. In logic synthesis, the RTL, SDC, and UPF, now fully verified both statically and dynamically, are mapped to technology gates. Power-specific isolation, level shifter, and retention cells are mapped to gates as well, where timing, area and power are all part of the cost function for generating a Netlist and associated UPF’. DFT insertion occurs as well, often simultaneously during this time. Once the Netlist and UPF’ are complete, another round of checks is done statically and dynamically at this level – once clean, the results are input to physical Implementation. In physical implementation, floorplanning is done with macro placement and power routing in mind. Then placement is performed where power switches are physically inserted and placed; and iterations of placement, routing estimation, logical optimizations, and clock tree synthesis are performed to once again trade off for timing, area, and power. Finally, the routing step occurs, where pre-route of the priority signals (clock, power enables, switch connections) is done followed by detailed routing of the rest of the design – all with emphasis on reducing power more granularly, while still trying to meet the timing and area targets.
UPF consistency should once again be checked during signoff. However, this time with the Netlist and UPF’ from logic synthesis and PGNetlist and UPF” from physical implementation. This will ensure that the connections and changes made to the netlist and UPF are consistent and clean, and the power intent is preserved. Logical equivalence checks comparing RTL and UPF vs. Gates and UPF’ vs. PGNetlist and UPF” ensures the logical functionality is preserved. Finally, static timing analysis should be performed with UPF to ensure the design meets timing; and power analysis with detailed waveform behaviors to give accurate power estimation results.