VC SpyGlass Lint

Early in-depth structural and functional design analysis for logic designers

A multitude of coding styles, structural and electrical design issues can manifest themselves as design bugs and result in design iterations or silicon respins. Other tools may detect design bugs but often at late stages of design implementation, after a significant investment in time and effort has already been made. As design teams become geographically dispersed, consistency and correctness of design intent become a key challenge for chip integration teams. Emphasis on design reuse and IP integration requires that design elements be integrated and meet guidelines for correctness and consistency within a shorter span than necessary.

Download Datasheet Download White Paper

Introduction

The VC SpyGlass™ linting solution integrates industry-standard best practices with Synopsys’ extensive experience working with industry-leaders. Lint checks include design reuse compliance checks such as STARC and OpenMORE to enforce a consistent style throughout the design, ease the integration of multi-team and multi-vendor IP, and promote design reuse.

VC SpyGlass Lint uses advanced formal techniques to pinpoint deeper functional problems in RTL designs without requiring test benches or assertions. The integrated solution of traditional linting technology with formal technology leverages the comprehensive and widely used lint checks within formal flow resulting in noise reduction and improved accuracy of results. The Formal Aware lint coupled with the increased ease of use results in advanced debugging and interactivity.

Features and Benefits

Identify critical design issues in RTL with sophisticated static and dynamic analysis
GuideWare™ methodology documentation and rule-sets included
Integrated comprehensive set of electrical rules check to ensure netlist integrity
Enables design reuse compliance checks, such as STARC and OpenMORE to enforce a consistent style
Step-by-step framework to capture and automate customer specific design rules
Native integration with Verdi® provides a debug environment to enable easy cross-probing
Supports Verilog, VHDL, SystemVerilog and mixed-language designs
Tcl shell for efficient rule execution and design querying
SoC abstraction flow for faster performance and low noise