VC SpyGlass CDC

Industry leading, low noise clock domain crossing verification solution

With increasing complexity and large design sizes, achieving predictable design closure is a challenge, and clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens, or sometimes even hundreds, of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis. CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle and may even find their way into silicon, necessitating costly re-spins.

Download Datasheet

Introduction

VC SpyGlass™ CDC provides a comprehensive methodology with scalable capacity for quality signoff with high debug productivity.

VC SpyGlass CDC correlates control and data signals resulting in a good understanding of the design intent for the lowest possible noise. It has also integrated structural and functional CDC analysis and enables formal based functional CDC analysis. Users also have the flexibility to generate System Verilog Assertions to verify CDC protocols and assumptions made for structural analysis.

SpyGlass RTL Signoff Chart with clock domain crossing verification on the chart

Features and Benefits

Highest performance and capacity to achieve faster signoff
Machine learning based Root Cause Analysis
Consistency with Design Compiler®, SpyGlass® and PrimeTime® use models
Automatic extraction for clock, reset and clock domains information from constraints
Better signoff quality with comprehensive structural and functional CDC analysis using formal and simulation based solutions
Protocol-independent analysis for synchronizers and auto-detection of quasi-static signals for lower false violations
Native support for UPF and SDC based CDC analysis
Native Verdi® integration for CDC centric debug
Hierarchical flows for fast turnaround using signoff abstract model