VC SpyGlass CDC

With increasing complexity and large design sizes, achieving predictable design closure is a challenge, and clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens, or sometimes even hundreds, of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis. CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle and may even find their way into silicon, necessitating costly re-spins.