- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
< Silicon Design & Verification
Silicon Design & Verification
< Products
< Products
< Products
< Products
< Products
< Products
< Products
< Silicon Design & Verification
< Solutions
< Solutions
Cloud
Synopsys in the Cloud
< Solutions
< Solutions
Optical Design Solutions
Lighting Simulation Software
Optical Design Software
Automotive Lighting Design Software
< Solutions
< Solutions
< Silicon Design & Verification
< Resources
< Resources
Verification
Articles
Blogs
Datasheets
Events
News
Newsletters
Success Stories
Videos
Webinars
White Papers
< Resources
< Silicon Design & Verification
< Services
< Services
< Services
< Silicon Design & Verification
< Community
Community
Community Overview
< Community
< Community
< Community
< Community
< Silicon Design & Verification
< Training
< Silicon Design & Verification
Training
Training and Education
< main menu
< Silicon IP
Silicon IP
< Products
< Products
Processor Solutions
ARC Processor IP
Embedded Vision Processor IP
Development Tools
Operating Systems
Ecosystem
ASIP Tools
< Products
Memories & Libraries
Logic Libraries
Memory Compilers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Products
< Products
Analog IP
Data Converters
< Products
< Products
< Products
< Silicon IP
< Markets
< Silicon IP
Newsletter
< Silicon IP
Customer Success
< Silicon IP
News
< Resources
< Resources
< main menu
< Software Integrity
Polaris Platform
Comprehensive application security from developer to deployment
< Software Integrity
< Software Integrity
< Software Integrity
Professional Services
Strategy and programs that address security before, during and after development
< Software Integrity
< Tools
< Tools
< Tools
< Tools
< Software Integrity
< Services
Managed Security Testing
Managed SAST
Dynamic Analysis (DAST)
Penetration Testing
Mobile Application Security Testing
Network Security Testing
< Services
Professional Services
Strategy and Planning
Architecture & Design
DevSecOps Integration
Cloud Security
Industry Solutions
< Services
< Software Integrity
< Training
< Training
Product Education
< Training
Community
< Software Integrity
< Solutions
< Solutions
< Resources
< Resources
< Software Integrity
< Software Integrity
Customers
< Partners
< Partners
Become a partner
< Software Integrity
< Software Integrity
Blog
< main menu
< About Us
Company
< About Us
< About Us
About Us
About Us
< Investor Relations
< About Us
Investor Relations
Investor Relations
< Community
< About Us
Community
Community
< Newsroom
< About Us
Newsroom
Newsroom
< Resources
< About Us
Resources
Resources
< Careers
< About Us
Careers
Careers
< main menu
VC SpyGlass CDC
With increasing complexity and large design sizes, achieving predictable design closure is a challenge, and clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens, or sometimes even hundreds, of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis. CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle and may even find their way into silicon, necessitating costly re-spins.
Introduction
VC SpyGlass™ CDC provides a comprehensive methodology with scalable capacity for quality signoff with high debug productivity.
VC SpyGlass CDC correlates control and data signals resulting in a good understanding of the design intent for the lowest possible noise. It has also integrated structural and functional CDC analysis and enables formal based functional CDC analysis. Users also have the flexibility to generate System Verilog Assertions to verify CDC protocols and assumptions made for structural analysis.
Features and Benefits
- Highest performance and capacity to achieve faster signoff
- Machine learning based Root Cause Analysis
- Consistency with Design Compiler®, SpyGlass® and PrimeTime® use models
- Automatic extraction for clock, reset and clock domains information from constraints
- Better signoff quality with comprehensive structural and functional CDC analysis using formal and simulation based solutions
- Protocol-independent analysis for synchronizers and auto-detection of quasi-static signals for lower false violations
- Native support for UPF and SDC based CDC analysis
- Native Verdi® integration for CDC centric debug
- Hierarchical flows for fast turnaround using signoff abstract model
Download