With increasing complexity and large design sizes, achieving predictable design closure is a challenge, and clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens, or sometimes even hundreds, of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis. CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle and may even find their way into silicon, necessitating costly re-spins.
VC SpyGlass™ CDC provides a comprehensive methodology with scalable capacity for quality signoff with high debug productivity.
VC SpyGlass CDC correlates control and data signals resulting in a good understanding of the design intent for the lowest possible noise. It has also integrated structural and functional CDC analysis and enables formal based functional CDC analysis. Users also have the flexibility to generate System Verilog Assertions to verify CDC protocols and assumptions made for structural analysis.
Faster Closure with Reduced Setup and Debug using Advanced RTL Static Signoff Platform
Shift Left Verification with Comprehensive Lint Signoff
Achieving CDC Signoff on Multi Billion Gate Designs with Hierarchical CDC Flow
VC SpyGlass CDC: Constraint-Based Verification of Clock Domain Crossings
VC SpyGlass RDC: Exhaustive Verification of Reset Domain Crossings