Verification White Paper Download

VC SpyGlass Lint: Early, Automated Detection of Design Issues

Contemporary chip designs contain a wide variety of functional errors and other design issues that may affect the quality of the end product. These range from inefficient or risky coding practices in register transfer level (RTL) design descriptions to complex hardware-software interaction bugs that show up only when running production applications. The goal of functional verification is to find all problems as early in the development process as possible. The commonly cited “rule of ten” states that it is ten times as much cost and effort to find and fix a bug as one moves from block-level design to chip-level verification (pre-silicon) and then to the bring-up lab and production use in the field (post-silicon). Even within the design phase, it is best to find issues as early as possible. This white paper focuses on the categories of problems that can be found very early in the development process using linting technology, and specifically the capabilities of Synopsys VC SpyGlass Lint.

Please complete the following form then click 'continue >>' to complete the download.   Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Job Title:Required
Postal/Zip Code:Required