VC SpyGlass RDC

Comprehensive, smarter and faster low noise reset verification

A well known source of metastability is caused by clock domain crossings; however, asynchronous reset crossings within the same clock domain can also cause metastability. The use of asynchronous resets is becoming more prevalent because of the broader use of multi-phase power-up boot sequences and increasing software stack adding to software asynchronous resets. Reset domain crossing (RDC) verification has become equally essential signoff criteria to ensure that the designs work per the specifications.


VC SpyGlass™ RDC is built on the highly scalable VC SpyGlass RTL Signoff platform that provides a comprehensive methodology with scalable capacity for quality signoff with high debug productivity. In addition, power domains add to the complexity of reset domain crossing and performing RDC analysis on UPF instrumented RTL (ie. True connection of switches and ISO devices) is a requirement to achieve the highest quality and most comprehensive signoff.

SpyGlass RTL Signoff Chart with clock domain crossing verification on the chart

Features and Benefits

  • Uses trusted industry standard static engines
  • Automatically extracts the clocks and resets for the designer's review 
  • Advanced RDC capabilities, like intricate reset relationships, reset to clock relationships, RDC qualifiers
  • Low-noise methodology to skip the reset-less sequential elements
  • Ability to reuse Design Compiler®, PrimeTime®, and Synopsys VCS® setup
  • Fine-grained control to the user to adapt to specific RDC methodology
  • Provides high-performance and efficient debug capabilities using Tcl
  • Native Verdi® integration for design debug
  • Native SDC support for RDC analysis
  • Integrated platform that encompasses Lint and CDC solutions as well