StarRC

Golden Signoff Parasitic Extraction

The StarRC™ solution is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal. memory IC  and 3DIC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows along with debugging capability delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. StarRC comes with in-built fieldsolver Rapid3D™, which can serve as a reference or provide higher accuracy measurements. 2.5D and 3D-IC extraction is also supported by StarRC.

Industry leading parasitic extraction for digital and custom design

Honey I Shrunk the Semiconductor

PODCAST: Listen to Amelia Dalton of EEJournal and Ruben Molina discuss modeling standards.

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Product Highlights

  • Foundry gold standard for extraction accuracy with broadest qualification and adoption
  • Leader in advanced modeling, including FinFET and color-aware multi-patterning at 10nm/7nm/5nm and beyond
  • High performance and capacity for gate and transistor-level extraction, enabled by multi-core distributed processing and simultaneous multi-corner (SMC) extraction
  • Inductance extraction for high frequency digital RLC clock net analysis
  • Self and mutual inductance extraction for RF, Power, Custom blocks
  • 2D Substrate extraction for substrate modeling 
  • 2.5D and 3D-IC extraction for interposer and stacked die technologies
  • Unified Rapid3D fast field solver for critical net, IP and custom circuit extraction 
  • Advanced flexible netlist reduction features for faster simulation turn-around time
  • Tightly integrated with industry leading Fusion Compiler™, IC Compiler™ II and PrimeTime® solutions for faster full-flow ECO turn-around time
  • Integration with IC Validator physical verification, CustomSim™/FineSim™/HSPICE® circuit simulators, Synopsys Custom Compiler ™ and other third-party solutions for increased designer productivity
  • Parasitic explorer enables visual debugging of the layout