Golden Signoff Parasitic Extraction
The StarRC™ solution is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal. memory IC and 3DIC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows along with debugging capability delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. StarRC comes with in-built field solver Rapid3D™, which can serve as a reference or provide higher accuracy measurements. 2.5D and 3D-IC extraction is also supported by StarRC.