Parasitic Extraction

StarRC™ is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal and memory IC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.

Industry leading parasitic extraction for digital and custom design

Honey I Shrunk the Semiconductor

PODCAST: Listen to Amelia Dalton of EEJournal and Ruben Molina discuss modeling standards.

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  • Foundry gold standard for extraction accuracy with broadest qualification and adoption
  • Leader in advanced modeling, including FinFET and color-aware multi-patterning at 10nm/7nm and beyond
  • High performance and capacity for gate and transistor-level extraction, enabled by multi-core distributed processing and simultaneous multi-corner extraction
  • Tightly integrated with industry leading IC Compiler™ II and PrimeTime® solutions for faster full-flow ECO turn-around time
  • Unified Rapid3D fast field solver for critical net, IP, and custom circuit extraction
  • Advanced netlist reduction features for faster simulation turn-around time
  • Inductance extraction for high frequency digital RLC clock net analysis
  • 3D-IC extraction solution for interposer and stacked die technologies
  • Integration with IC Validator physical verification, CustomSim circuit simulation, Synopsys Custom Compiler and other third party implementation and custom design solutions for increased designer productivity