StarRC for Custom Design

Custom Design is evolving as the semiconductor process technology and design methodology make a shift to address the growing need for Custom SoCs. EDA tools have to enable these Custom Design requirements so that chip designers can push the performance envelope. StarRC™  is the golden signoff extraction tool and has recently introduced new features to improve TAT & QoR for Custom Design flow. 

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Key Features

Inductance Extraction

Historically, capacitance was the primary component extracted since designs were most sensitive to capacitance. Then came resistance extraction and now self and mutual inductance are being extracted. Power, RF, SerDes, high speed I/O and 3D-IC are driving the necessity for inductance extraction since the frequency band of operation is pushed higher in the GHz region. StarRC can do window or net based inductance extraction and provide a netlist in SPF or s-parameter format.

Design Inductor

High frequency designs routinely utilize on chip inductors as a design element and as frequencies get pushed higher, accurate design of these inductors is very critical. StarRC can be used to extract inductance model for these design inductors providing confidence to the designer.

Resistance Field Solver

Power, Display driver and 3D-IC designs are driving the need for all angle routing on the chip. Traditionally Manhattan or 45-degree shapes were supported by extraction tools. StarRC now has a Resistance Field Solver to support all angle extraction.

Netlist Reducer

With increasing complexity and integration in SoCs comes an increase in transistor count. When this is coupled with the additional parasitic components that need to be extracted for higher accuracy, detailed netlist becomes impractical to simulate. Hence, the role of netlist reducers, whether standalone or part of the extraction tool or simulator, have become a critical component of custom design analysis. StarRC Netlist Reducer provides the flexibility to reduce different portions of the circuit individually keeping results accuracy vs reduction trade-off in mind. Simulation speed-up and reduced memory footprint are the benefits of including StarRC Netlist Reducer in your design flow.

Interactive RC Reporting

Keeping up with the shift-left methodology in EDA world, StarRC has introduced Interactive RC reporting to improve designer productivity. Custom layout designers can measure R & C for traces on the fly thus improving the quality of the layout before it is extracted and simulated.

Parasitic Explorer

Once the layout has been extracted over several process corners, post-layout parasitic analysis is dictated to improve overall TAT by reducing simulation iterations. This is where StarRC Parasitic Explorer comes in for command line or GUI based post layout parasitic exploration & analysis. It enables designers to do what-if-analysis, RC scaling, the ability to compare parasitics, open/short debug, etc.