In electronic design automation (EDA), parasitic extraction (PEX) is calculation of the parasitic effects in both the designed devices and the required wiring interconnects of an electronic circuit: parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasitic devices, parasitic components, or simply parasitics.

The major purpose of parasitic extraction is to create an accurate analog model of the circuit, so that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as: 

Analog circuits are often run in detailed test benches to indicate if the extra extracted parasitics will still allow the designed circuit to function.

Parasitic Extraction Figure 1  | Synopsys
Parasitic Extraction Figure 2  | Synopsys

Different Categories of Parasitics

On a typical semiconductor die you can categorize the parasitics in 3 categories:

  1. Front-end of the Line (FEOL). Parasitics associated with the semiconductor devices.
  2. Middle-end of the Line (MEOL). Parasitics associated with the contacts on semiconductor devices.
  3. Back-end of the Line (BEOL). Parasitics associated with the interconnect layers.

How Does Parasitic Extraction Work?

There are two types of engines which can be used for parasitic extraction:


Fields Solver Based

In this method, the PEX engine solves Maxwell’s equations to calculate the parasitic R, C, L or K. This method is referred to as 3D extraction. It is a higher accuracy method than the rule-based method, but also takes more processing power and is not used for full-chip extraction. Within the field solver category, you could have finite element or random walk algorithm being employed – tradeoff being processing time vs. accuracy, finite element algorithm being more accurate.

Parasitic Extraction Figure 3  | Synopsys

Rule Based

In this method, the PEX engine uses a look up table to calculate the parasitic R or C. This method is referred to as 2D or 2.5D extraction. It can support full-chip extraction.

Parasitic Extraction Figure 4  | Synopsys

Parasitic Extraction and Synopsys

Synopsys offers parasitic extraction solutions for both digital and custom design environments:

StarRC™ solution is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal. memory IC  and 3DIC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows along with debugging capability delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. StarRC comes with in-built field solver Rapid3D™, which can serve as a reference or provide higher accuracy measurements. 2.5D and 3D-IC extraction is also supported by StarRC.

QuickCap NX is the golden extraction reference tool based on high accuracy 3D Field Solver which is well suited for advanced 14nm FinFET and beyond process technologies. Embedded 3D device visualizer makes it ideal for process exploration. High accuracy extraction, reference tool to rule based extractor, standard cell characterization, memory cell characterization and enhancing PDK quality are some of the key applications served by QuickCap NX.

Raphael is the gold standard, 2D and 3D resistance, capacitance and inductance extraction tool for optimizing on-chip parasitic for multi-level interconnect structures in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide.

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