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Industry Panel: Optimizing Memory in Multi-Die Architectures
Date: Dec 09, 2024
Multi-die designs have emerged as the next big disruption in computing to cater to the unsatiable need for larger, faster, and more energy efficient compute systems. For such high-performance computing systems there is a need for memories to perform at peak levels, while optimizing power, performance, area, and cost.
Watch this panel to hear Ansys, Micron, Synopsys, and Western Digital discuss:
- The different memory chip design and verification approaches for multi-die designs
- The use of HBM and other memory technologies in 2.5 and 3D packaging
Watch On-Demand
Featured Speakers
Murat Becer
VP Product, Ansys
Raghu Sreeramaneni
Director of HBM Architecture, Micron
Sutirtha Kabir
R&D Engineering Sr Director, Synopsys
Huijuan Wang
Sr. Director VLSI Design Engineering, Western Digital
Moderator
William Wong
Senior Content Director, Electronic Design
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