Intel Corporation, headquartered in Santa Clara, California, is one of the world's largest semiconductor chip manufacturers by revenue. Founded on July 18, 1968, by Gordon Moore and Robert Noyce, Intel has significantly advanced semiconductor technology, supplying microprocessors for most computer system manufacturers and developing the x86 series of instruction sets used in many PCs. The company also produces chipsets, network interface controllers, flash memory, GPUs, FPGAs, and other computing and communication devices.

At the Intel Innovation 2023 conference, Intel and Synopsys demonstrated the world's first Universal Chiplet Interconnect Express (UCIe) interoperability test chip, showcasing robust UCIe traffic between their respective UCIe PHY IPs, marking a notable advancement in multi-die system design.

Intel Logo


The development of multi-die systems involves several key challenges:

  • Silicon Manufacturing Time: Manufacturing silicon and validating its functionality is time- and cost-intensive.
  • Design Planning: Extensive planning is required, especially for re-using package or board designs.
  • Interoperability Confidence: Ensuring that different components from various vendors can work seamlessly together.
  • Process Node Partitioning: Mitigating the expense of manufacturing at advanced nodes by partitioning designs to include multiple process nodes.


To address these challenges, Intel and Synopsys collaborated on a UCIe-connected chiplet-based test chip:

  • Test Chip Design: Intel's test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology, paired with a Synopsys UCIe IP test chip fabricated on the TSMC N3 process.
  • Pre-Silicon Validation:  Synopsys VCS® functional verification solution was used to simulate each test chip and uncover issues pre-silicon.
  • UCIe Interoperability: The successful pairing of the test chips demonstrates the commercial viability of mixing and matching dies in real-world multi-die systems


The collaboration between Intel and Synopsys resulted in several key outcomes:

  • Interoperability Proof Point: The test chip demonstration provides a solid proof point for mixing and matching IP designs, laying the foundation for an open chiplet ecosystem.
  • Custom Silicon Innovation: UCIe enables the integration of dies from different vendors and process nodes, supporting advanced packaging technologies and fostering new waves of custom silicon innovation.
  • Reliability and Testability: UCIe IP includes verification IP, built-in testability features, cyclic redundancy checks (CRC), and retry functionality to ensure reliable die-to-die connectivity.

Through their ongoing collaboration, Intel and Synopsys are working to enable widespread adoption of multi-die systems, helping chip designers meet the performance demands of AI, connectivity, and cloud computing in today's digital world.