System-on-chip (SoC) designs continue to increase in complexity and move to advanced nodes to meet the connectivity and functionality demands of today’s smart everything applications. This results in aggressive optimizations, increasing die sizes, and more sophisticated architectures. To meet ambitious design needs while facing shrinking time-to-market windows and the already-challenging prospect of catching errors throughout the design and testing process, design teams need to constantly push the limits of power, performance, and area (PPA).
Functional verification tools can help detect and correct some of these errors. However, with the push to optimal PPA, engineers often need to scale down optimizations to sacrifice quality of results (QoR). A more predictable technique is needed to respond quickly to frequent, unexpected functional changes and determine if an alternate design representation would behave the same way as a verified version.
This is where the concepts of formal equivalence checking and functional engineering change order (ECO) come in.
Read on to learn more about the basics of equivalence checking and functional ECO, current challenges in the equivalence checking process, and its many benefits. You’ll also gain some perspectives into how Synopsys’ unique, machine learning (ML)-powered equivalence checking approach and Synopsys Formality® ECO solution deliver an array of advantages compared to traditional techniques, and some insights into where the future is headed.