In the context of an SoC flow, a functional engineering change order (ECO) is a method to directly patch, or modify the gate-level, post synthesis version of a design. The reason for this modification could include fixing an error that was discovered in the RTL (pre-synthesis) version of the design, applying optimization to the design or updating the design based on a new customer requirement.

The post-synthesis version is patched directly to avoid the costly and time-consuming process of completely re-implementing the design, which includes logic synthesis, technology mapping, place, route, layout extraction, and timing verification. EDA tools provide the ability to reduce the scope of tasks such as synthesis to only the portions impacted by the ECO, thus saving time. These tools can also verify equivalence of the RTL and patched gate-level implementation using formal methods.

How Does Functional ECO Work?

When presented with a functional ECO, there are three items to consider when automating the process:

  1. Determining the minimum portion of the RTL that will require re-synthesis
  2. Determining the smallest area (patches) that needs to be iterated
  3. Verifying the correctness of the result, taking into account the structural changes that an ECO can create

The figure below illustrates the process:

Functional ECO Process | Synopsys

What are the Benefits of Functional ECO?

Functional ECOs provide a critical late-stage optimization step for any design. This is where errors are corrected, optimization is applied, and late-stage customer requests are accommodated. Since this process occurs late in the design cycle, there is significant risk regarding the introduction of an error that will escape to silicon, creating a very costly and time-consuming problem.

Functional ECO automation can dramatically reduce the chances of an error escape. The specific benefits include:

  • Efficiency. The ECO is implemented with the minimum amount of re-work.
  • Time-to-market. Since these changes occur near tapeout, delays can translate into a late to market problem if not handled well.
  • Confidence. Intelligent logic equivalence checking (LEC) ensures the changes have not modified the behavior of the chip in an unintended way.

Functional ECO Automation Challenges

Since functional ECOs are typically applied to the design late in the process, there is less opportunity to verify and optimize these changes. Essentially, the changes need to be “right from the start”. Some challenges to overcome include:

  • Efficiency of the patch. An inefficient process will add a lot new logic to the netlist, which can cause routing congestion and timing issues.
  • Optimized synthesis. If the re-targeted RTL isn’t focused properly in the key areas requiring re-synthesis, the process will take too long and time-to-market can be impacted.
  • Robust verification. Logic equivalency checking (LEC) is typically applied to the original design and the patched design to verify there are no unintended consequences of the ECO. Some ECOs can perform optimizations that make LEC difficult (e.g., datapath optimization).

Functional ECO and Synopsys

Synopsys Formality ECO provides a new and robust way of implementing functional ECOs. Formality ECO delivers faster turn-around time, smaller patches and better quality of results. The figure below summarizes these benefits:

Formality ECO: New way of doing functional ECOs | Synopsys

Synopsys PrimeECO is the industry’s first signoff-driven ECO closure solution that achieves signoff closure in a single cockpit.

Synopsys ECO Fusion builds on the fused signoff capabilities by reducing the need for excessive ECO iterations by allowing rapid design changes during the physical implementation phase with IC Compiler II, resulting in faster timing convergence and reducing the design cycle by up to 30%.

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