Functional ECOs provide a critical late-stage optimization step for any design. This is where errors are corrected, optimization is applied, and late-stage customer requests are accommodated. Since this process occurs late in the design cycle, there is significant risk regarding the introduction of an error that will escape to silicon, creating a very costly and time-consuming problem.
Functional ECO automation can dramatically reduce the chances of an error escape. The specific benefits include:
- Efficiency. The ECO is implemented with the minimum amount of re-work.
- Time-to-market. Since these changes occur near tapeout, delays can translate into a late to market problem if not handled well.
- Confidence. Intelligent logic equivalence checking (LEC) ensures the changes have not modified the behavior of the chip in an unintended way.