In the context of an SoC flow, a functional engineering change order (ECO) is a method to directly patch, or modify the gate-level, post synthesis version of a design. The reason for this modification could include fixing an error that was discovered in the RTL (pre-synthesis) version of the design, applying optimization to the design or updating the design based on a new customer requirement.
The post-synthesis version is patched directly to avoid the costly and time-consuming process of completely re-implementing the design, which includes logic synthesis, technology mapping, place, route, layout extraction, and timing verification. EDA tools provide the ability to reduce the scope of tasks such as synthesis to only the portions impacted by the ECO, thus saving time. These tools can also verify equivalence of the RTL and patched gate-level implementation using formal methods.