ESP Technology

ESP Technology

High Coverage Symbolic Verification

ESP’s symbolic simulation technology verifies the equivalence between reference and implementation models with high design coverage. ESP performs this verification in different flavors e.g. Verilog versus SPICE, Verilog versus Verilog (e.g. behavioral Verilog to RTL) Liberty Compiled DB versus Verilog or SPICE versus SPICE. ESP works at native transistor level without abstraction for planar, FDSOI, FinFET and Gate All Around technologies. With a formal equivalence check engine under it’s hood, ESP can verify the equivalence between the models with a few automatically generated symbolic vectors with  high design coverage and enables customers to catch the most corner case design bugs. 

ESP is most often used to verify custom and compiled memories – SRAM, ROM, TCAM as well as standard cells and IOs. Along with a functional verification to verify the mission mode operation, ESP has the following powerful capabilities:

Power Integrity Verification

ESP Power Integrity Verification detects common low-power and power-down errors and generates SPICE vectors for analysis and debug. IT improves low-power design verification by detecting common low-power design errors and expanding power-down and sleep-mode failure detection. Power integrity verification mode uses dynamic symbolic vectors to unearth corner case power issues that compliments standard static power checkers. These capabilities include detecting:

  • Missing/incorrect level shifts
  • Missing/incorrect isolation circuitry
  • Power/Ground shorts
  • Sneak paths between supplies

Redundancy Verification

ESP Redundancy Verification technology can inject faults in the rows and/or columns of the memory and prove that the redundancy implementation corrects failures as intended. For successfully validated serial and parallel redundancy schemes ESP produces a fault repair table with fuse connections. If the redundancy scheme is not validated successfully then a counter example is provided to debug the redundancy scheme failure.

Scan Chain Verification

ESP Scan Chain verification mode proves the scan chain order is identical between design representations (RTL, gates, schematic SPICE netlist). Additionally, this mode verifies the transition back and forth between functional mission mode and scan mode, the respective parallel and serial loading of the scan chain through either mode and the serial shifting of the scan chain symbols in each design view to determine the scan chain order.

Library Verification

With ESP’s library verification capability customers functionally verifies equivalence for standard cells reference and implementation models (e.g. Verilog, SPICE and Liberty compiled DB). The verification of the library can be done quickly using ESP’s distributed processing capability. Library verification can be setup through ESP’s automatic reading of constraints from the compiled DB. The SiliconSmart®  ESP integration provides a setup handoff to verify cells with ESP that are created by SiliconSmart®

Interactive Signal Tracing

Interactive Signal Tracing provides a powerful environment for transistor-level debug. It allows users to query the cause of any transition, back-trace causal paths, and identify the source of X-values.

ESP Interactive Signal Tracing (IST) Technology provides unique features to help debug verification errors by back-tracing the events on SPICE nets to the design inputs enabling the debug of points that look incorrect or have suspicious values.

  • Simple command-based interface
  • Back traces nets in schematic design
  • Track internal signal transitions
  • Report calculated transistors strengths