ESP’s symbolic simulation technology verifies the equivalence between reference and implementation models with high design coverage. ESP performs this verification in different flavors e.g. Verilog versus SPICE, Verilog versus Verilog (e.g. behavioral Verilog to RTL) Liberty Compiled DB versus Verilog or SPICE versus SPICE. ESP works at native transistor level without abstraction for planar, FDSOI, FinFET and Gate All Around technologies. With a formal equivalence check engine under it’s hood, ESP can verify the equivalence between the models with a few automatically generated symbolic vectors with high design coverage and enables customers to catch the most corner case design bugs.
ESP is most often used to verify custom and compiled memories – SRAM, ROM, TCAM as well as standard cells and IOs. Along with a functional verification to verify the mission mode operation, ESP has the following powerful capabilities: