ESP Technology

Library Verification

Library Verification provides a powerful environment that brings library cell verification capabilities into ESP Shell for a large group of simple matched designs. 

Power Integrity Verification

ESP Power Integrity Verification detects common low-power and power-down errors and generates SPICE vectors for analysis and debug. IT improves low-power design verification by detecting common low-power design errors and expanding power-down and sleep-mode failure detection. These capabilities include detecting:

  • Missing/incorrect level shifts
  • Missing/incorrect isolation circuitry
  • Power/Ground shorts
  • Sneak paths between supplies

Redundancy Verification

ESP Redundancy Verification technology enables quick verification of redundancy logic used in embedded RAM designs that was implemented to bypass failing cells. ESP-CV allows users to inject "faults" into the bit-cells to represent errors, and then performs an analysis to confirm that there is a redundant row/column decoder configuration which "corrects" the faulted cell.

When a bit cell cannot be corrected, ESP generates a counter-example pattern sensitizing the failure so that it can be further analyzed. ESP-CV can confirm the simultaneous correction of "N" errors.

Interactive Signal Tracing

Interactive Signal Tracing provides a powerful environment for transistor-level debug. It allows users to query the cause of any transition, back-trace causal paths, and identify the source of X-values.

ESP Interactive Signal Tracing (IST) Technology provides unique features to help debug verification errors by back-tracing the events on SPICE nets to the design inputs enabling the debug of points that look incorrect or have suspicious values.

  • Simple command-based interface
  • Back traces nets in schematic design
  • Track internal signal transitions
  • Report calculated transistors strengths 

Power-up Re-initialization

The Power-up Re-initialization feature allows for the re-initialization of certain nodes within the powered-down portion of a design when power is reapplied.

The Power-up Re-initialization feature allows users to assign values on nets that otherwise would come up in an "X" state upon power-down and power-up, avoiding the time consuming and inefficient process of hand editing the test bench to force certain net states. Users can specify the nets that should be re-initialized to a defined state when a user-defined re-initialization condition is met.