Power Optimization in Design Compiler
Power Compiler™ automatically minimizes power consumption at the RTL and gate level, and enables concurrent timing, area, power and test optimizations within the Design Compiler® synthesis solution. It performs advanced clock gating and low power placement to reduce dynamic power consumption, and performs leakage optimization to reduce standby power. Power Compiler along with Design Compiler Graphical utilizes concurrent multi-corner multi-mode (MCMM) optimization to reduce iterations and provide faster time-to-results. With power intent defined by the standardized IEEE 1801 Unified Power Format (UPF), designers can use Power Compiler to implement advanced low power techniques such as multi-voltage, power gating, and state retention.