VC Verification IP for DDR3

Synopsys® VC Verification IP for the JEDEC DDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on DDR3 based designs. VC VIP DDR3 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP DDR3 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.

DDR3 VC Verification iP

DDR3 SDRAM and DIMM Protocol Features

  • JESD79-3F DDR3, JESD79-3-1A-01 DDR3L and JESD79-3-2 DDR3U JEDEC
  • SDRAM device standards
  • MRAM support
  • 512Mb to 8Gb densities and x4, x8 and x16 wide SDRAM devices
  • BL switch on the fly, 8 banks, 8 bit pre-fetch
  • Write leveling, read leveling, jitter, auto self refresh
  • Address mirroring
  • Delay modeling : Fly by Delay, Trace Delays, Pre and Post buffer delays
  • DFI monitor