EDA
System
IP
SolvNetPlus
Training & Education
Synopsys Verification IP (VIP) for ONFI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of ONFI based designs.
Highlights
- Native SystemVerilog/UVM
- Runs natively on all major simulators
- Runtime JEDEC and vendor part selection
- Built-in coverage model
- Built-in protocol and timing checks
- Verdi protocol-aware debug
- Overriding timing parameters
- Backdoor memory access
- Bypass initialization
- Error injection and exceptions
- Trace files and debug ports
- Configuration creator GUI
Key Features
- Supports up to ONFI 5.0 specification
- All mandatory commands
- All optional commands
- All training commands
- Single and dual bus operations
- All Timing modes
- Configurable number of
- Target
- LUNs per Target
- Blocks per LUN
- Pages per Block
- Bytes per Page
- ECC mechanism using Hamming code
- Support run time frequency change
- Passive monitor support
- Access to internal states of the model
- Analysis port for score-boarding
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