Synopsys® VC Verification IP for JEDEC UFS provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of UFS links operating in high speed and low speed modes.
VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences. Time to Market can be reduced with UFS Host testsuite and UFS Device testsuite which contain a rich set of testcases which are CTS complaint and can be used as a plug and play solution to validate the DUT.