VC Verification IP for DDR5

Synopsys® VC Verification IP for JEDEC DDR5 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DDR5/4/3/2 based designs.

This VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. It is natively integrated with Verdi® Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottlenecks.

The availability of Synopsys' design-proven DDR5 VIP delivers a new level of confidence to end customers by enabling verification closure of industry-first JEDEC 1.0 DDR5 devices."

Malcolm Humphrey


Vice President of Marketing, Micron

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

Verification IP for DDR5


  • Native SystemVerilog/UVM/OVM
  • Memory model certification
  • Access to vendor specifications and memory models
  • Runs natively on all major simulators
  • All JEDEC parts
  • Runtime JEDEC and vendor part selection
  • Verification plan and coverage
  • Built-in protocol and timing checks
  • Verdi Protocol and Memory Analyzer
  • Dynamic reconfiguration
  • Backdoor memory/mode registers access
  • Bypass/fast initialization
  • Error injection & exceptions
  • Trace file and debug ports for easy debug
  • Delay modeling: fly by delay, trace delay, buffer delays
  • DIMM and DRAM level monitors

Key Features

  • DDR5 DRAM JEDEC rev 0.99
  • 3DS rev 0.99
  • RDIMM (RCD01 rev 0.9)
  • LRDIMM (DB01 rev 0.85)
  • All speed bins
  • All densities (8Gb to 32Gb)
  • All DRAM data widths (4, 8, 16)
  • All commands, and burst sizes (BC8/BL32 and on the fly BL)
  • Sequential and wrap addressing
  • SDR/DDR modes
  • Clock stop/frequency change
  • PDA, MPSM and 2N mode
  • CA parity and ECC
  • Trainings (CS, CA, read training pattern, read preamble training, write leveling)
  • All mode registers
  • On die termination (ODT)
  • PPR, DFE
  • Partial write, write pattern
  • Refresh schedule monitoring, configurable refresh rates, refresh management (RFM)
  • DQS interval oscillator