Verification IP for DDR5

Specifications

• DDR5 MRDIMM MRCD02: Rev0.99_R0, DDR5 MRDIMM MDB02:  Rev0.98 v2, DDR5: Rev2.12_R1, DDR5 RCD05/06: RCD06_Rev0.7 r0, DDR5 MRDIMM Gen3  (MRCD03): Rev0.7_R1, DDR5 CSODIMM JESD82-531A.01-DDR5CKD01

Interfaces: Discrete DRAM, DIMMs (CSODIMM/ MRDIMM/ RDIMM/ UDIMM/ SODIMM)

Key VIP Features

• Noise and Jitter modelling on the DQS/DQ bus
• Analysis Port, Bypass/Skip Initialization
• Static/dynamic timing and configuration settings
• Callback Hooks for CMD and Data completion, Backdoor Access (Register and Data), Error Injection
• Performance statistics
• Support for DFI Monitor

Debug and Analysis

• Verdi protocol and performance analysis
• Protocol/timing checks
• Trace Files for CMD & data
• Debug ports for CMD, addresses, RCD mode, FSM state
• Detailed error messages (expected vs observed) with specs section

Key Protocol Features

• DDR5 DRAM, 3DS, UDIMM, RDIMM
  • Speed bins up to 9200 Mbps; densities 8Gb–64Gb
  • x4/x8/x16 widths; all bank group orgs
  • 3DS: up to 16 logical ranks
  • All mandatory commands, burst sizes, mode registers
  • PDA, MPSM, 2N mode, CA inversion/parity, CRC, masking
  • Custom RD/WR preambles, Read DQS offset
  • ODT, MPC, init flow, freq change
  • Trainings: CS, CA, read/write leveling
• DDR5 UDIMM/RDIMM
  • Up to 2 ranks, dual channel
  • Parity, power down, self-refresh
  • RCD registers, SDR/DDR mode
  • DCA/DCS & QCA/QCS training
• DDR5 CSODIMM
  • PLL modes: Bypass, Single, Dual
  • Device & reset initialization
  • Clock stop, frequency change
  • Control words, board/output/propagation delays
• DDR5 MRDIMM (Mux-Mode)
  • Data rate: up to 16,000 Mbps
  • x4/x8; 2/4 ranks; 1N & 2N mode
  • Initialization, CRC (DQ/DCA), Scrambler
  • Clock phase sync, DQS interval oscillator
  • All PHY trainings (DCS, DCA, MRD, MWD, DWL, MRE)
  • HIT-SR
• DDR5 MRDIMM (Rank-Mode)
  • Data rate: up to 9,200 Mbps
  • x4/x8; 2/4 ranks; 1N & 2N mode
  • Initialization, PHY trainings (DCS, DCA)
  • HIT-SR
• DDR4 UDIMM, RDIMM, LRDIMM, DDR4 3DS, MRAM
  • Data rates: 1600–3200 Mbps; Densities: 1Gb–16Gb
  • All commands & mode registers
  • Trainings: Write leveling, Read preamble
  • Gear Down, MPSM, Per-DRAM addressability, Jitter
  • Write CRC, CA parity, MPR, DBI & masking
  • Address mirroring
  • Temperature-controlled refresh
  • Bank group, fine-granularity & self-refresh abort
  • Delay modeling: Fly-by, trace, pre/post buffer
  • Core timings
• DDR3 MRAM, UDIMM, RDIMM, LRDIMM
  • Data rates: 800–2133 Mbps; Densities: 512Mb–8Gb
  • All commands & mode registers
  • BL switch on the fly, 8 banks, 8-bit prefetch
  • Trainings: Write leveling, Read leveling
  • Jitter, Auto self-refresh
  • Address mirroring
  • Delay modeling: Fly-by, trace, pre/post buffer
  • Core timings
• DDR2
  • Data rates: 400–800 Mbps; Densities: 64Mb–8Gb
  • All commands & mode registers
  • Write burst interrupt
  • Override logical address formatting
  • Core timings