Verification IP for HBM4/3/2E/2

Specifications: HBM4 (JESD270-4​ rev 1.0), HBM3 (JESD238 rev 2.1), HBM2e/2 (JESD235D rev 2.60)

Interfaces: JEDEC (Single channel, Multi channel)

DUT Types/Topology: Memory Controller and Memory Phy

Key VIP Features

• Single/Multi channel HBM4/3/2E/2, DFI MC/PHY/Monitor component   
• Specification linked Functional coverages and Verification Plan
• Noise and Jitter modelling on the DQS/DQ bus
• Analysis Port, Bypass/Skip Initialization
• Static/dynamic timing and configuration settings
• Callback Hooks for CMD and Data completion, Backdoor Access(Register and Data), Error Injection
• Performance statistics

Debug and Analysis

• Verdi protocol and performance analysis
• Protocol and Timing Checks
• Trace File: Command and Data
• Debug Ports: Commands, Bank/Row/Column addresses, MR address/opcode, Main/Bank FSM state, RL, WL
• Detailed Error Message : Ref specs section, Expected Vs Observed 

Key Protocol Features

• HBM4
  • All data rates up to 8000 Mbps support for JEDEC , Data rates upto 14400Mbps for vendor datasheets
  • Density of (3Gb, 4Gb, 6Gb, 8Gb, 9Gb,12Gb and 16Gb per Pseudo channel) , Stack Id (4Hi, 8Hi,12Hi and 16Hi) , Bank Group (16 Bank Group with 64 Banks)
  • All Command(ACTIVATE, READ, WRITE, PRECHARGE/REFRESH/RFM/SREF/PDE/PDX)and Mode registers (RL, WL, PL, WPAR, Cattrip, Loopback)
  • Dual Clocking architecture with WDQS to CK ratio 4:1
  • IEEE 1500 mode support
  • HBM trainings (AWORD/DWORD MISR, WDQS2CK Alignment , DQS Oscillator, DQS Oscillator)
  • Configurable Multi Channel Support (upto 32 DRAM per channel)
  • On Die ECC, ECS, DCA, DCM, DBI, Parity, Refresh Management(DRFM), Self repair
• HBM3
  • All data rates up to 8000 Mbps support for JEDEC , Data rates upto 9600Mbps for vendor datasheets
  • Density of (1Gb, 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 9Gb, 12Gb and16Gb per Pseudo channel) ,Stack Id (8Hi, 12Hi and 16Hi) ,Bank Group (16 Bank Group with 64 Banks)
  • All Command(ACTIVATE, READ, WRITE, PRECHARGE/REFRESH/RFM/SREF/PDE/PDX)and Mode registers (RL, WL, PL, RAS, RTP, RFM)
  • Dual Clocking architecture with WDQS to CK ratio 4:1
  • IEEE 1500 mode support
  • HBM trainings (AWORD/DWORD MISR, WDQS2CK Alignment , DQS Oscillator)
  • Configurable Multi Channel Support (upto 16 DRAM per channel)
  • On Die ECC, DCA, DCM, DBI, Parity, Refresh Management
• HBM2E/2
  • All data rates(1.0 Gbps/pin to 3.6Gbps/pin) including vendor datasheets support
  • Memory Densities per channel(2Gb to 24Gb)
  • All Command(MRW/MRR, RD/WR, ACTIVE)and Mode registers (WL/RL, Preamble/Postamble)
  • ECC, Bank Grouping, DBI, Data Masking
  • IEEE 1500 mode support
  • Data Read/Write and command parity support
  • Configurable refresh rates, Temperature derating
  • HBM2E variant support with test mode and command sampling