VC Verification IP for HBM

Synopsys® VC Verification IP for HBM provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of HBM based designs.

HBM VC Verification IP

Protocol Features

  • JEDEC JESD23B rev 2.10
  • HBM1 and HBM2 modes
  • IEEE Test port supported
  • All commands - ROW/COLUMN commands sampling
  • All mode register implementation
    • Burst length BL2 and BL4 
    • All combination of read and write latencies
  • DBI read and DBI write
  • Data masking (for write)
  • Sequential and wrap addressing
  • Refresh operation and corrupting the data if refresh not received
  • Seamless read and write
  • Bank group
  • Frequency change and clock stop
  • Pseudo channel
  • Data read/write and command parity
  • ECC support