VC Verification IP for DDR2

Synopsys® VC Verification IP for DDR2 provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of DDR2 designs.

DDR2 VC Verification IP

Protocol Features

  • JEDEC JESD79-2E DDR2 SDRAM device standard
  • Configurations for memory vendors and randomization to model all possible legal JEDEC parts
  • Specify part details at runtime
  • Includes DFI monitor
  • Write leveling, Read leveling, Jitter, Auto Self Refresh
  • Address mirroring
  • Delay modeling: Fly by Delay, Trace Delays, Pre and Post buffer delays
  • Override timing parameters and clock
  • Override logical address formatting as per application level address of host
  • Bypass and fast-memory initialization to reduce simulation time
  • Backdoor access to memory contents and mode registers
  • Debug port for high level of abstractions—logical address, commands, states