VC Verification IP for LPDDR4

Synopsys® VC Verification IP for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR4 based designs. VC VIP LPDDR4 is integrated with Verdi Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand view of memory operations along with a consolidated view of the entire memory address space. VC VIP LPDDR4 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests. In addition to providing LPDDR protocol verification, the Synopsys LPDDR4 VIP can be dynamically configured to model any memory vendor component.

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

LPDDR4 VC Verification IP

LPDDR4 SDRAM Protocol Features

  • 4Gb to 32Gb densities and x16 SRAM devices
  • Write leveling, DQ Read Training and ZQ Calibration
  • Directed per bank refresh for concurrent bank operation, Data Bus Inversion (DBI)
  • Power Off Sequence, Self Refresh, Deep Power Down, Partial Array Self-Refresh

LPDDR4 SDRAM Verification Features

  • Bypass and Fast Memory initialization
  • Error injection
  • Configurable timing
  • Extensive protocol and timing checks
  • Built-in functional coverage
  • Backdoor access to memory contents