VC Verification IP for HMC

Synopsys® VC Verification IP for HMC provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of HMC designs.

HMC VC Verification IP

Protocol Features

  • HMC specification 2.0
  • Single/multi-link (1, 2 & 4)
  • Chaining
  • Lane polarity and lane inversion
  • Complete initialization - clock recovery, scrambler/descrambler
  • Merging of the request and response for easier debug
  • Request and response logging based on the access
  • Performance statistics
  • Models the vault and DRAM delay user control to vary delay
  • Complete control to user for out of order and in order response
  • All HMC commands (Atomic Read/Write , Mode Read/Write)
  • Call backs for error response and link retry
  • Runtime reset, asymmetric lane
  • Poisoning, warm reset, retraining
  • Power management
  • Access to register space via backdoor, I2C and JTAG interface