Cloud native EDA tools & pre-optimized hardware platforms
Synopsys® VC Verification IP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on DDR4 based designs. VC VIP DDR4 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP DDR4 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.