VC Verification IP for SPI (Bus, Flash, SafeSPI)

Synopsys® VC Verification IP for SPI (Serial Peripheral Interface) Bus, Flash, and SafeSPI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification closure of SPI Bus, Flash, and SafeSPI based designs.

Verification IP for SPI/QSPI

Highlights

  • Native SystemVerilog/UVM
  • Runs natively on all major simulators
  • Runtime JEDEC and vendor part selection for SPI Flash
  • Board propagation IO delay modeling
  • Verification plan and coverage
  • Built-in protocol and timing checks
  • Verdi protocol-aware debug
  • Trace file for easy debug
  • Error injection and exceptions

Key Features

  • SPI Bus, Flash and SafeSPI
  • SafeSPI for Automotive safety
  • Motorola, National Semiconductor Microwire and Texas Instrument SSP modes
  • SPI Flash Memory Vendor part numbers
  • Multi I/O, 8 lanes (Dual/Quad/Octal)
  • Master and Slave configurations
  • All SPI operating modes
  • Register Data Width (8/16/32)
  • Bit and byte endianness
  • Payload size control and data value control
  • Baud rate control for Master Agent
  • Configurable length for Instruction, Address, and Data Phase
  • Configurable lane count for Instruction, Address, and Data Phase
  • Configurable timers (Leading, Trailing, and Idle time between transfer)