EDA
System
IP
SolvNetPlus
Training & Education
Synopsys Verification IP (VIP) for eMMC also supports UHS-II/SD-TRAN and provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification closure of UHS-II/ SD-TRAN based designs. VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, example tests, and functional coverage. VIP is natively integrated with Verdi® Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug.
Highlights
- Native SystemVerilog/UVM
- Optional source code test suite
- Runs natively on all major simulators
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi protocol-aware debug
- Overriding timing parameters
- Backdoor memory access
- Bypass initialization
- Error injection and exceptions
- Trace files and debug ports
- Configuration creator GUI
Key Features
- UHS-II Addendum v.1.02, 1.01
- Host and Card Model
- UHS-II Layering (Link and Transaction layers)
- Data Width( 8 and 16 Bits)
- FD Mode (Block and Byte Mode)
- HD mode
- Low Power mode
- GO_DORMANT_STATE
- NO_PHY_MODE, LOCAL_PHY_MODE and REMOTE_PHY_MODE
- CCMD, DCMD, MSG (FCREQ, FCRDY and STAT) commands
- INQUIRY_CONFIG and SET_COMMON_CONFIG
- Configuration Register
- UHS-II SD_TRAN supported
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