Verification IP for UFS

Specifications

• JEDEC UFS v5.0/4.0/3.x/2.x
• JEDEC UFS HCI v4.0
• JEDEC UME v1.1/1.0,JESD224
• MIPI UniPro v3.0r0.4/2.0/1.8/1.6
• MIPI MPHY v6.0r04/5.0/4.x/3.0

Interfaces: MPHY RMMI (10/20/40/80 bit)/Serial Interface at PHY

DUT Types/Topology: Host Controller, UFS Device, Phy & Unipro

Key VIP Features

• API control for HCI driver
• Built-in protocol compliance checks
• Layered architecture supports all UniPro and Mphy layers

Debug and Analysis

• Verdi based protocol and performance analysis
• Transaction log​, verbosity messages​ & debug ports

Key Protocol Features

• CPORT signaling (64/128 bit)
• DME support for all UniPro Layers
• Access and configurability of all MPHY attributes
• Multiple outstanding Command UPIU

Task Management Request/Response

Controllable Logical Unit Command Depth

Resets: Hardware, Endpoint, Host UniPro warm reset, Logical reset

Universal Memory Extension (UME) support RPMB

Lane-to-lane Skew Injection

Unipro

• CPORT interface (128/64 bit) on application side, RMMI (10/20/40/80 bit) or Serial on PHY side.
• Access and configurability of all M-PHY attributes
• Up to 4 TX and 4 RX lanes and asymmetric number of TX and RX lanes
• Complete DME support
• Transfer message, Packet, frame and Symbols
• HS Link startup

Mphy

• Lane management layer
• M-PHY VIP as M-PHY Model
• CTRL and DATA  SAPs
• External/internal SYNC
• Automatic filler, Marker insertion, LCC support

Test Suites / Groups Features

• JESD224A CTS Tests
• Supports register-level read/write via sequencer
• Includes interrupt aggregation functionality
• Covers compliance, complex UFS, and UniPro physical layer tests (e.g., power mode, test mode, hibernate)
• Simulates fatal error conditions and validates recovery per spec.
• Generates all HCI error scenarios
• Dedicated test cases to generate Host UIC Error Code Register coverage for each layer