VC Verification IP for MIPI SPMI

Synopsys® VC Verification IP for MIPI SPMI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI SPMI designs. 

MIPI SPMI VC Verification IP

Protocol Features

  • Master and slave components implementing power controller and power management IC
  • Multi-master and multi-slave topologies
  • Device enumeration — master and slave
  • Bus arbitration — configurable bus owner master
  • Command, data, address and no response frames
  • Parity, ACK/NACK, bus park cycle
  • Master connection and disconnection
  • Master and slave external control signals
  • Command sequences