VC Verification IP for MIPI SPMI

Synopsys VC Verification IP for MIPI SPMI provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MIPI SPMI designs.

VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences. 

Verification IP for MIPI SPMI


  • Native SystemVerilog/UVM
  • Runs on all major simulators
  • Verification plan and coverage
  • Built-in protocol checks
  • Verdi protocol-aware debug
  • Error injection and exceptions

Key Features

  • SPMI 2.0, 1.0
  • Master and slave components implementing power controller and power management IC
  • Multi-master and multi-slave topologies
  • Device enumeration — master and slave
  • Bus arbitration — configurable bus owner master
  • Command, data, address and no response frames
  • Parity, ACK/NACK, bus park cycle
  • Master connection and disconnection
  • Master and slave external control signals
  • Command sequences